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7360213 Method for promotion and demotion between system calls and fast kernel calls  
Described is an enhanced application of a fast kernel trap, or kernel function call, in combination with a kernel system call providing a system of handling complications during kernel thread...
7359998 Low-power CD-ROM player with CD-ROM subsystem for portable computer capable of playing audio CDs without supply energy to CPU  
A low-power audio CD player for portable computers permits operation of the CD-ROM subsystem when power is not being supplied to the computer subsystem. In one embodiment of the invention, the...
7340547 Servicing of multiple interrupts using a deferred procedure call in a multiprocessor system  
A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether...
7337253 Method and system of routing network-based data using frame address notification  
A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for...
7337254 Information processing system and method of controlling the same  
An information processing system operating in response to a remote control signal transmitted from a remote controller, the information processing system including a remote signal receiver to...
7334063 Method and device for register access according to identifier register  
A method for accessing digital data information is used for reducing accessing time when a processor accesses digital data from a register. The method comprises the steps of accessing data from a...
7330926 Interruption control system  
An interruption control system includes a PIC, an APIC and a power management unit disposed in a south bridge chip of a computer system. In response to the triggering of an interrupt status...
7328294 Methods and apparatus for distributing interrupts  
The present invention relates to handling interrupts in a multiprocessor system. An interrupt controller can receive input from a variety of interrupt sources, such as peripheral components and...
7321945 Interrupt control device sending data to a processor at an optimized time  
An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use by the CPU and an interrupt...
7320038 Method and apparatus for interfacing a LAN to a drive  
An interface card connects a LAN with a drive. The interface card comprises a dual port memory interface, which interfaces to the main control card of the drive. An interrupt line informs a...
7315911 Method for efficient inter-processor communication in an active-active RAID system using PCI-express links  
A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a...
7305588 Testing the interrupt sources of a microprocessor  
A method of testing the interrupt sources of a microprocessor having a number of interrupts which are each operable to execute an interrupt service routine when enabled, each interrupt having a...
7302512 Interrupt steering in computing devices to effectuate peer-to-peer communications between device controllers and coprocessors  
A computer device, an input/output ("I/O") communication subsystem, a chipset and a method are disclosed for implementing interrupt message packets to facilitate peer-to-peer communications...
7302511 Chipset support for managing hardware interrupts in a virtual machine system  
In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to...
7299379 Maintaining cache integrity by recording write addresses in a log  
An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system...
7299312 Telecommunication apparatus  
A transition module using an input/output (I/O) bus interface can be connected to a backplane having a bus connector. The transition module is provided with an external connector for receiving an...
7299350 Internet protocol security decryption with secondary use speculative interrupts  
A system for improved decryption performance includes a computer in electronic communication with an encrypted network. A controller performs a decryption operation on an encrypted packet received...
7290076 Optmizing an interrupt-latency or a polling rate for a hardware platform and network profile combination by adjusting current timer values for both receive and transmit directions of traffic and calculating a new timer value to be used for both receive and transmit directions of traffic  
Provided are techniques for determining a timer value. An advised number of packets per interrupt for both receive and transmit directions of traffic is determined. Current timer values for both...
7281268 System, method and computer program product for detection of unwanted processes  
A system, method and computer program product are provided which are capable of intercepting a call. Once intercepted, it is determined whether the call is associated with a previous sequence of...
7281074 Method and apparatus to quiesce USB activities using interrupt descriptor caching and asynchronous notifications  
In one embodiment, a data processing system includes, but is not limited to, a processor, a memory coupled to the processor, and a universal serial bus (USB) controller coupled to the processor...
7281073 Method for controlling interrupts and auxiliary control circuit  
An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt...
7278062 Method and apparatus for responding to access errors in a data processing system  
In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error...
7275122 Method and system for maintaining a desired service level for a processor receiving excessive interrupts  
A method and system for maintaining a desired service level for a processor receiving excessive interrupts. The method includes the operation of defining an interrupt processing period during...
7269678 Interrupt request program and microcomputer  
An interrupt controller specifies and outputs the most highly prioritized one of a plurality of interrupt signal requested for output. A CPU executes a process corresponding to an interrupt signal...
7269677 Power consumption reduction and quicker interruption response in an information processing device utilizing a first timer and a second timer wherein the second timer is only conditionally activated  
An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes...
7263568 Interrupt system using event data structures  
Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a state of an event data structure. The...
7263567 Method and apparatus for lowering the die temperature of a microprocessor and maintaining the temperature below the die burn out  
According to one embodiment, a method is disclosed. The method includes determining whether the temperature of a central processing unit (CPU) exceeds a predetermined threshold. In addition, the...
7260663 System and method for presenting interrupts  
An information processing system is provided which includes an interrupt table including a plurality of entries relating to interrupts requested by entries in a plurality of event queues. The...
7257655 Embedded PCI-Express implementation  
Methods and apparatus provide PCI Express support on a programmable device. A device includes a hard-coded transceiver that supports functionality associated with the PCI Express physical layer...
7254726 System and method for managing system events by creating virtual events in an information handling system  
In a computer system or information handling system, a virtual system event provides for the communication of the notification of a system events from the hardware of the computer system to the...
7248146 Method for waking a device in response to wireless network activity  
A method and a system for data transmission between a first electronic device and a second electronic device, wherein the second electronic device is in a sleep mode. Transmission of data between...
7243084 Information processing method and apparatus for billing  
An information processing apparatus for receiving data, such as content data. During the time the content data is being downloaded by a terminal over a communication network, the volume of...
7243178 Enable/disable claiming of a DMA request interrupt  
Machine-readable media, methods, and apparatus are described for performing direct memory access (DMA) transfers. In some embodiments, a device may generate an interrupt to request a DMA transfer....
7240137 System and method for message delivery across a plurality of processors  
A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue...
7237041 Systems and methods for automatic assignment of identification codes to devices  
A system and method for automatically and uniquely assigning identification codes to a plurality of slave processors. A master processor having communication port is linked to a first slave...
7237051 Mechanism to control hardware interrupt acknowledgement in a virtual machine system  
In one embodiment, a method includes recognizing an interrupt pending during an operation of guest software, determining that the interrupt is to cause a transition of control to a virtual machine...
7222203 Interrupt redirection for virtual partitioning  
The present disclosure relates to the handling of interrupts in a environment that utilizes virtual machines, and, more specifically, to the steering of interrupts between multiple logical...
7222204 Testing the interrupt priority levels in a microprocessor  
A method of testing the priority levels of the interrupt sources of a microprocessor having a number of interrupt sources which are each operable to execute an interrupt service routine when...
7222251 Microprocessor idle mode management system  
An idle mode system has a clock gating circuit, a bus interface unit, memory interfaces and an interrupt and idle control unit. The clock gating circuit receives a first clock and designated...
7222347 Method and apparatus for processing real-time events associated with a wireless communication protocol  
A processor may perform real-time event processing of real-time events in a manner that enables a radio module equipped computer system to operate in accordance with a wireless communication...
7216346 Method and apparatus for managing thread execution in a multithread application  
A method for managing the suspension and resumption of threads on an individual basis in an information handling system having an operating system (OS) kernel and a user process having multiple...
7216189 Single BIOS technique for supporting processors with and without 64-bit extensions  
A technique according to the invention enables a single BIOS to support processors with or without 64-bit extensions efficiently. The BIOS creates a data structure having entries that correspond...
7213153 Application program interface interception system and method  
A method of intercepting application program interface, including dynamic installation of associated software, within the user portion of an operating system. An API interception control server in...
7209994 Processor that maintains virtual interrupt state and injects virtual interrupts into virtual machine guests  
In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is...
7209993 Apparatus and method for interrupt control  
An interrupt control apparatus comprising an interrupt vector register for holding address information corresponding to interrupt resources of a first type which are managed by an operating system...
7206883 Interruption control system and method  
An interruption control system includes a first input/output interruption controller, a second input/output interruption controller, and an interruption control device bus. The first input/output...
7203786 Error-flagging apparatus, systems, and methods  
Apparatus and systems, as well as methods and articles, may operate to monitor a flag bit to indicate an occurrence of at least one of a plurality of operational excursions associated with a...
7200701 System and method for processing system management interrupts in a multiple processor system  
A system and method for processing system management interrupts in multiple processor systems is disclosed. In one embodiment, a method for processing a system management interrupt (SMI) in an...
7200694 Servicing multiple hot-plug events utilizing a common event signal in providing hot-plug attention button support  
Each attention button is tied to a presence signal, which is also used to detect the presence of a PCI adapter card within a slot. By comparing HPPC register states, pending due to a system...
7197587 Systems-events core for monitorings system events for a cellular computer system within a parent computer system, system-event manager for monitoring system events for more than one cellular computer system, and related system and method  
A system-event core for monitoring system events in a cellular computer system within a parent computer system is provided. The system-event core comprises: a control register block for each cell...