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7487274 Method and apparatus for generating unique identification numbers for PCI express transactions with substantially increased performance  
A method and apparatus for generating identification numbers for PCI Express that provides unique generation and substantially increased system performance. A system having a PCI Express fabric...
7480755 Trap mode register  
Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector...
7478390 Task queue management of virtual devices using a plurality of processors  
A task queue manager manages the task queues corresponding to virtual devices. When a virtual device function is requested, the task queue manager determines whether an SPU is currently assigned...
7475398 System and method for implementing a smart system call  
According to the present invention, a “smart system call” may be implemented. The smart system call employs a code “stub” that is used to make function calls to privileged memory locations. The...
7472214 Real-time embedded simple monitor method and computer product  
A processor context stored in a stack area at a time of an interrupt occurrence is saved in a context saving area of an ICB corresponding to an ISR that is interrupted. The ISR corresponding to...
7472396 Extensible event notification mechanism  
An extensible event notification system detects certain events, and notifies requestor programs that have registered to receive such notification. The system includes a notification manager,...
7469309 Peer-to-peer data transfer method and apparatus with request limits  
Methods and apparatus for peer-to-peer data transfers in a computing environment provide configurable control over the number of outstanding read requests by one peer device to another. A...
7464211 Method of detecting and recovering a lost system management interrupt (SMI) in a multiprocessor (MP) environment  
A method for handling multiple system management interrupt (SMI) events in a multiprocessor system. The method comprises a first set of one or more processors in the multiprocessor system...
7463671 Rake receiver interface  
In some embodiments of the present invention, a method and apparatus to generate interrupts in a transfer of information between a rake receiver and a processor, said interrupts having a rate of...
7461247 Method for transitioning control of a peripheral device from a first device driver to a second device driver during operating system initialization  
A system for meeting demanding boot time requirements, such as those timing requirement mandated by vehicle telematics systems, is described. Current computer systems use expensive hardware like...
7457514 Television apparatus embedded with optical disk device  
An television apparatus embedded with an optical disk device includes a television unit having a microcomputer for a television and a power source for a television and an optical disk unit having...
7454547 Data exchange between a runtime environment and a computer firmware in a multi-processor computing system  
A method, system, apparatus, and computer-readable medium for exchanging data between an application program and a firmware in a computer system having multiple CPUs are provided. According to the...
7447818 System and method for controlling remote console functionality assist logic  
A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality...
7447820 Retargeting of platform interrupts  
Systems, methods, and apparatus to retarget platform interrupts in a reconfigurable system. Some embodiments include identifying each processor of a multiprocessor system capable of processing...
7447819 Information processing apparatus and SMI processing method thereof  
An information processing apparatus includes: a CPU; a controller including a signal transmission unit configured to supply an SMI (system management interrupt) signal to the CPU; a...
7444639 Load balanced interrupt handling in an embedded symmetric multiprocessor system  
In an embedded symmetric multiprocessor (ESMP) system it is desirable to maintain equal central processing unit load balance. When an interrupt occurs, a single central processing receives the...
7444449 Method, computer program product and computer system for controlling execution of an interruption routine  
A method, a computer program product and a computer system for controlling the execution of an interruption routine for interrupting an active application. The computer system may include a first...
7444450 Method and system for detecting excessive interrupt processing for a processor  
A method and system is provided for detecting excessive interrupt processing for a processor. The method includes the operation of defining an interrupt processing period during which measuring of...
7444385 Global interrupt and barrier networks  
A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating...
7441076 Data storage apparatus that appropriately revises FDCB information during background formatting  
A data storage apparatus, including a controller that formats a rewritable recording medium in the background, interrupts the background formatting when a host computer requests to store data in...
7433985 Conditional and vectored system management interrupts  
An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode...
7434224 Plural operating systems having interrupts for all operating systems processed by the highest priority operating system  
Multiple different operating systems are enabled to run concurrently on the same computer. A first operating system is selected to have a relatively high priority (the realtime operating system,...
7430629 Internet SCSI communication via UNDI services  
A method and system for emulating a hardware Internet Small Computer System Interface (iSCSI) Host Bus Adapter (HBA) without risking an interruption of communication between a computer and a...
7428609 Method and system to partition hardware resources between operating systems  
Disclosed is a method and system to partition hardware resources between operating systems. A determination is made whether a first PCI resource attached to a line of a bus is to be sequestered to...
7426728 Reducing latency, when accessing task priority levels  
One embodiment disclosed relates to a method of reducing access latency to a task priority register (TPR) of a local programmable interrupt controller unit within a microprocessor. A command is...
RE40497 Communication system which dynamically switches sizes of sample buffer between first size for quick response time and second size for robustness to interrupt latency  
An apparatus for and method of implementing a novel buffer ba full duplex communication system is disclosed. The disclosed invention is particularly useful in native sign processing systems...
7421527 Transmission apparatus and transmission method  
A small-sized and low-cost transmission apparatus and a transmission method (having a high responsivity) capable of transmitting an interrupt signal with a small number of input/output terminals...
7421431 Providing access to system management information  
System management information may be obtained from multiple input devices associated with system management mode drivers during pre-boot and during runtime of an operating system. The system...
7418555 Multiprocessor system and method to maintain cache coherence  
A multiprocessor system may have a plurality of processors and a memory unit. Each of the processors may include at least one cache memory. The memory unit may be shared by two of the processors....
7415558 Communication steering for use in a multi-master shared resource system  
New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is...
7415730 Microcomputer and test method therefore  
When a test mode signal is rendered active by a signal given from an external terminal, a CPU reads and runs various self-testing programs stored in a ROM. When any of the test programs comes to a...
7415557 Methods and system for providing low latency and scalable interrupt collection  
A method for processing an interrupt signal within a microprocessor based system is described. The method includes storing a received interrupt signal within an interrupt cause register of an...
7409506 Multiprocessor system with high-speed exclusive control  
A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and...
7398371 Shared translation look-aside buffer and method  
A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an...
7398378 Allocating lower priority interrupt for processing to slave processor via master processor currently processing higher priority interrupt through special interrupt among processors  
In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP)...
7395434 Method for secure storage and verification of the administrator, power-on password and configuration information  
A computer includes a processor, an input device and a read only memory (“ROM”). One or more passwords are flashed in the ROM in encoded form. The encoding process may include any well-known...
7395362 Method for a slave device to convey an interrupt and interrupt source information to a master device  
A computer system, more generally a master-slave system, may be configured with interrupt handling capability without additional dedicated interrupt lines. An interrupt condition may be bound with...
7389496 Condition management system and a method of operation thereof  
For use with a processor employing a hierarchical register consolidation structure (HRCS), a condition management system and method of operation thereof. In one embodiment, the system includes a...
7389368 Inter-DSP signaling in a multiple DSP environment  
The invention includes a method and apparatus for synchronizing a first processor with a second processor. The method includes storing in a register parallel bits of data from the first processor,...
7386646 System and method for interrupt distribution in a multithread processor  
A system and method for interrupt distribution in a multithread processor are disclosed. A connection between an interrupt and a set of thread processors can be programmed. When the interrupt is...
7386640 Method, apparatus and system to generate an interrupt by monitoring an external interface  
In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over...
7386647 System and method for processing an interrupt in a processor supporting multithread execution  
A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to...
7380275 Secure and backward-compatible processor and secure software execution thereon  
A secure processor assuring application software is executed securely, and assuring only authorized software is executed, monitored modes and secure modes of operation. The former executes...
7379418 Method for ensuring system serialization (quiesce) in a multi-processor environment  
A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one...
7373448 Method, system, and program for building a queue to test a device  
Provided are a method, system, and device for signaling a reconnection inhibitor over a bus to cause the reconnection inhibitor to access the bus to inhibit an Input/Output (I/O) controller from...
7370130 Core logic device of computer system  
A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC...
7370193 Computing system being able to quickly switch between an internal and an external networks and a method thereof  
The invention discloses a computing system such as a computer, a Personal Digital Assistant, or a mobile phone, being connected both to an internal network and an external network and being able...
7363410 Flexible interrupt handling methods for optical network apparatuses with multiple multi-protocol optical networking modules  
An API including an interrupt handler registration function and one or more interrupt dispatchers, is provided to an optical networking apparatus to facilitate registration of interrupt handlers...
7363407 Concurrent arbitration of multidimensional requests for interrupt resources  
The present invention relates to a system and methodology to facilitate negotiation, assignment, and management of interrupt resources in a flexible and dynamic manner. An interrupt arbitration...
7363409 Interrupt control system and method for reducing interrupt latency  
An interrupt control system is disclosed. The interrupt control system can include control logic that provides at least one interrupt request signal to a processor in response to at least one...