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7606961 Computer system and data pre-fetching method  
A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a...
7603489 Direct memory access controller including first and second transfer setting registers  
DMAC includes current transfer setting registers and next transfer setting registers. Each of the current transfer setting registers stores transfer source address, transfer destination address and...
7581039 Procedure and device for programming a DMA controller in which a translated physical address is stored in a buffer register of the address processing unit and then applied to the data bus and stored in a register of the DMA controller  
A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base...
7568055 Data processing apparatus for selecting either a PIO data transfer method or a DMA data transfer method  
The image processing apparatus (data processing apparatus) stores data in a storing unit (storing means), inputs and outputs the data to and from the storing unit via a storage control unit...
7565460 Information processing apparatus and method for handling packet streams  
A control machine which uses a data amount stored in an FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the...
7557949 Inkjet print control apparatus  
An inkjet print control apparatus connected with a processor and a memory through a bus. The memory stores print image data. The inkjet print control apparatus fetches the print image data stored...
7549002 Enclosure numbering in RAID data storage systems  
Enclosure numbering is performed in redundant array of independent disk (RAID) data storage systems. If first, second, and third boards in an enclosure indicate a first enclosure number, the...
7548997 Functional DMA performing operation on DMA data and writing result of operation  
In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read...
7546392 Data transfer with single channel controller controlling plural transfer controllers  
A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer...
7546391 Direct memory access channel controller with quick channels, event queue and active channel memory protection  
A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes...
7546386 Method for virtual resource initialization on a physical adapter that supports virtual resources  
A method for directly sharing a network stack offload I/O adapter that directly supports resource virtualization and does not require a LPAR manager or other intermediary to be invoked on every I/O...
7539782 Method of virtualizing I/O resources in a computer system  
A method of virtualizing hardware resources in a multiprocessor computing environment is provided. Each resource is provided a resource address. A hardware resource map is provided to store virtual...
7533198 Memory controller and method for handling DMA operations during a page copy  
A memory controller provides page copy logic that assures data coherency when a DMA operation to a page occurs during the copying of the page by the memory controller. The page copy logic compares...
7523229 Memory protection during direct memory access  
An I/O controller to which an I/O device is connected includes a DMA controller (DMAC) and an access control unit (ACU). The DMAC executes DMA transfer in accordance with data transfer control...
7496695 Unified DMA  
In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The...
7467239 Method and system for programming a DMA controller in a system on a chip, with the DMA controller having source, destination, and size registers  
A procedure is provided for programming a DMA controller of a system on a chip that includes a CPU, an MMU, a DMA controller including source, destination, and size registers, and entities that are...
7464199 Method, system, and program for handling Input/Output commands  
Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device...
7464198 System on a chip and a method for programming a DMA controller in a system on a chip  
A method is provided for programming a DMA controller in a system on a chip. According to the method, a memory management unit translates a programming virtual address into a programming physical...
7464197 Distributed direct memory access for systems on chip  
A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct...
7451248 Method and apparatus for invalidating cache lines during direct memory access (DMA) write operations  
A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The...
7450131 Memory layout for re-ordering instructions using pointers  
Embodiments include storing graphics instructions at addresses in a memory in an original order, and storing in the memory pointers associated with each instruction pointing to the addresses of the...
7444441 Device including means for transferring information indicating whether or not the device supports DMA  
A device for attachment to a host for serial data communication including means for transferring to the host a predetermined data structure indicating whether or not the device supports direct...
7426588 Storage apparatus  
In a data input/output with other apparatus, a data transfer controller (DTC) of a storage controller multiprocesses a data transfer with the other apparatus by utilizing a saving/recovering...
7415550 System and method for controlling DMA data transfer  
A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC...
7404015 Methods and apparatus for processing packets including accessing one or more resources shared among processing engines  
Methods and apparatus are disclosed for processing packets, for example, using a high performance massively parallel packet processing architecture, distributing packets or subsets thereof to...
7380115 Transferring data using direct memory access  
A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command...
7373437 Multi-channel DMA with shared FIFO  
A direct memory access (DMA) circuit ( 200 ) includes a read port ( 202 ) and a write port ( 204 ). The DMA circuit ( 200 ) is a multithreaded initiator with “m” threads on the read port ( 202...
7370150 System and method for managing a cache memory  
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and...
7370137 Inter-domain data mover for a memory-to-memory copy engine  
Address translation for a source and destination of the data that utilizes different page tables. A direct memory access (DMA) engine is used as a memory-to-memory copy engine by utilizing a...
RE40213 Methods and apparatus for providing direct memory access control  
Techniques are described for providing mechanisms of data distribution to and collection of data from multiple memories in a data processing system. The system may suitably be a manifold array...
7343434 Buffer management within SLS (simple load store) apertures for inter-endpoint communication in advanced switching fabric  
A single copy memory sharing scheme between multiple endpoints in an interconnect architecture may use a buffer management method in an advanced switching fabric having multiple endpoints that...
7334108 Multi-client virtual address translation system with translation units of variable-range size  
A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that...
7302699 Logged-in device and log-in device  
A management agent ME 1 of a target T 1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T 1 ...
7296139 In-memory table structure for virtual address translation system with translation units of variable range size  
A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that...
7293120 DMA module having plurality of first addressable locations and determining if first addressable locations are associated with originating DMA process  
A DMA module includes an address generator to perform a write or read access to a location of an addressable memory, and an address counter to advance a stored address to an adjacent memory...
7278008 Virtual address translation system with caching of variable-range translation clusters  
A virtual address translation table and an on-chip address cache are usable for translating virtual addresses to physical addresses. Address translation information is provided using a cluster that...
7266667 Memory access using multiple sets of address/data lines  
Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may be accessed independently, using...
7259876 Image processing apparatus, and, control method and control device therefor  
A first storage stores input image data. A second storage stores image data read from the first storage. A control part determines, with respect to a timing at which data transfer of image data...
7254690 Pipelined semiconductor memories and systems  
The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor...
7228367 Direct memory access controller for carrying out data transfer by determining whether or not burst access can be utilized in an external bus and access control method thereof  
An address region of an internal bus wherein a burst access can be utilized in an external bus is set in an address table. A DMA control unit determines whether or not a burst access can be...
7225287 Scalable DMA remapping on a computer bus  
A system for addressing bus components comprises a bus controller component that controls access between a CPU and a memory address space. A plurality of bus components connected to said bus...
7219169 Composite DMA disk controller for efficient hardware-assisted data transfer operations  
In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a...
7185121 Method of accessing memory via multiple slave ports  
A crossbar switch ( 12 ) arbitrates for access from multiple bus masters ( 14, 16, 18, 20 and 22 ) to multiple addressed slave ports ( 3 and 4 ) that have overlapping address ranges. In one...
7130933 Method, system, and program for handling input/output commands  
Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device...
7120708 Readdressable virtual DMA control and status registers  
Apparatus and method for carrying out a DMA transfer wherein an address is written into a DMA register of a DMA controller specifying a memory location within a memory device at which either the...
7110837 Control system and method for on-line editing of user program  
A control system includes a programmable controller having a CPU unit that carries out cyclic operations of processes. An additional temporary user memory is provided in addition to a regular user...
7103783 Method and system for providing data security in a file system monitor with stack positioning  
A System for providing data security in a first device driver operably installed in a computer operating system having a layered plurality of device drivers ( 81, 82, 83, 84 ) for accessing data in...
7080187 Bug segment decoder  
Disclosed are a system and method of forwarding bus transactions from a source device to a target device in multiple data bus enviroment. A bridge is coupled between a first data bus and a second...
7051123 Data transfer engine of a processor having a plurality of modules  
In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer...
7010633 Apparatus, system and method for controlling access to facilities based on usage classes  
An apparatus, system and method for controlling access to facilities based on usage class of a requestor are provided. With the apparatus, system and method, a two level protection mechanism is...
Matches 1 - 50 out of 234 1 2 3 4 5 >