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8185672 Transmission of data bursts on a constant data rate channel  
A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving...
8151007 Information processing program and information processing apparatus  
A computer of an information processing apparatus repeatedly accepts an operation to designate at least one of a plurality of command elements making up of a command, executes at least any one of a...
8141099 Autonomic method and apparatus for hardware assist for patching code  
Hardware assist to autonomically patch code. The present invention provides hardware microcode to a new type of metadata to selectively identify instructions to be patched for specific performance...
8127047 Storage system and its multiple extent exclusive control method  
Proposed is technology for shortening the time required for analyzing and processing commands issued from multiple hosts and speeding up the processing. When a controller receives a command...
8108571 Multithreaded DMA controller  
A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a...
8099528 Data filtering using central DMA mechanism  
A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an...
8055816 Memory controllers, memory systems, solid state drives and methods for processing a number of commands  
The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue...
8055807 Transport control channel program chain linking including determining sequence order  
A method, apparatus, and computer program product for processing a chain linked transport control channel program in an I/O processing system is provided. The method includes receiving a first...
8041847 Periodic and conditional execution of DMA operations  
Scheduling Direct Memory Access (DMA) operations. Blocks are provided in a first DMA chain, with each block in the first DMA chain corresponding to an operation and comprising a pair of pointers, a...
8037215 Performance evaluation of algorithmic tasks and dynamic parameterization on multi-core processing systems  
Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is...
8032663 Information processing system, information processing apparatus and integrated circuit chip  
There is provided an information processing system that includes an integrated circuit chip having stored therein a plurality of file systems, a first information processing apparatus that engages...
8006001 Method and apparatus for manipulating direct memory access transfers  
A mechanism is provided for removal of instructions for context re-evaluation. The mechanism receives an external request to perform the instruction remove. In response to this external request,...
7941574 CKD partial record handling  
A method for combining partial records into a single direct memory access (DMA) operation for a count key data (CKD) protocol in a computer environment is provided. In an initiator processor of the...
7937504 Transport control channel program message pairing  
A method, apparatus, and computer program product for processing a chained-pair linked transport control channel program in an I/O processing system is provided. The method includes receiving a...
7930444 Device and method for controlling multiple DMA tasks  
A method for controlling multiple DMA tasks, the method includes receiving multiple DMA task requests; the method is characterized by defining multiple buffer descriptors for each of a plurality of...
7917659 Variable length command pull with contiguous sequential layout  
The invention relates to a method for computer signal processing data and command transfer over an interface and more particularly to a communication between peripheral firmware and a host...
7899957 Memory controller having a buffer for providing beginning and end data  
A memory controller, such as a SDRAM controller, controls the way in which data is retrieved, in order to make more efficient use of the bandwidth of the memory data bus. More specifically, when a...
7890673 System and method for accessing non processor-addressable memory  
A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs,...
7890597 Direct memory access transfer completion notification  
Methods, systems, and products are disclosed for DMA transfer completion notification that include: inserting, by an origin DMA on an origin node in an origin injection FIFO, a data descriptor for...
7882277 Processor, data transfer unit, multicore processor system  
A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory...
7877523 Apparatus, computer program product, and system for completing a plurality of chained list DMA commands that include a fenced list DMA command element  
An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are...
7865631 Dynamic logical data channel assignment using time-grouped allocations  
A method, system and program are provided for dynamically allocating DMA channel identifiers to multiple DMA transfer requests that are grouped in time by virtualizing DMA transfer requests into an...
7853733 Operational circuit  
An operational circuit for performing an operation of an arbitrary number of input data pieces by using a DMA transfer according to a descriptor control and output results. The arbitrary number of...
7853727 Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection  
A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its...
7844752 Method, apparatus and program storage device for enabling multiple asynchronous direct memory access task executions  
A method, apparatus and program storage device for enabling multiple asynchronous direct memory access task executions. DMA I/O operations and performance are improved by reducing the overhead in...
7840717 Processing a variable length device command word at a control unit in an I/O processing system  
A computer program product, apparatus and method for processing a variable length device command word (DCW) at a control unit configured for communication with an input/output (I/O) subsystem in an...
7827331 IO adapter and data transferring method using the same  
An IO adapter for guaranteeing the data transfer bandwidth on each capsule interface when multiple capsule interfaces jointly share the DMA engine of the IO adapter. An IO driver containing a...
7822885 Channel-less multithreaded DMA controller  
A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a...
7818473 Embedded locate records for device command word processing  
A method of packaging locate record commands for device command word (DCW) processing is provided. A first locate record command is packaged into DCW prefix parameter data. The first locate record...
7814251 DMA transfer control system that performs data decode and data transfer and that generates a no operation (NOP) interrupt signal to end the DMA transfer processing in response to a NOP designation  
A direct memory access (DMA) transfer apparatus configured to sequentially read, into a register, at least one transfer setting value for data transfer stored in a memory and to perform DMA...
7805549 Transfer apparatus and method  
There is provided a transfer apparatus having a bridge that transfers a transaction between a first and a second bus, and a data transfer unit that performs a data transfer by DMA between the first...
7805548 Method, medium and system setting transfer unit corresponding to a minimum overhead in a data processing system  
A method, medium and system for setting a transfer unit in a data processing system. The method comprises setting a transfer unit in a data processing system which repeatedly performs a process of...
7805579 Methods and arrangements for multi-buffering data  
Embodiments may comprise logic such as hardware and/or code within a heterogeneous multi-core processor or the like to coordinate reading from and writing to buffers substantially simultaneously....
7793012 Information processing unit, system and method, and processor  
The invention is provided to improve the information processing efficiency of a multiprocessor system. An information processing apparatus 1000 comprises a main processor 200 for exercising...
7793295 Setting bandwidth limiter and adjusting execution cycle of second device using one of the GBL classes selected based on priority of task from first device  
Task management methods. A plurality of GBL (global bandwidth limiter) classes is provided. One of the GBL classes is selected based on the priority of a first task, in which the first task is from...
7769918 Apparatus and method for high performance volatile disk drive memory access using an integrated DMA engine  
A method and apparatus for high performance volatile disk drive (VDD) memory access using an integrated direct memory access (DMA) engine. In one embodiment, the method includes the detection of a...
7761617 Multi-threaded DMA  
A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n”...
7734843 Computer-implemented method, apparatus, and computer program product for stalling DMA operations during memory migration  
A computer-implemented method, apparatus, and computer program product are disclosed for migrating data from a source physical page to a destination physical page. A migration process is begun to...
7716404 Pseudo-full duplex communication using a half duplex communication protocol  
In a communication system having a master-slave arrangement communicating with each other using the RS485 protocol, an FPGA with a buffer memory is provided in the master and slave, respectively,...
7702742 Mechanism for enabling memory transactions to be conducted across a lossy network  
A network interface is disclosed for enabling remote programmed I/O to be carried out in a “lossy” network (one in which packets may be dropped). The network interface: (1) receives a plurality of ...
7698475 DMA transfer control apparatus for performing direct memory access transfer from a transfer source to a transfer destination  
A DMA transfer control apparatus comprises an internal memory for temporarily storing data, a buffer for temporarily storing data, a selector for selecting one of input data to the buffer and...
7694037 Information processing apparatus and command multiplicity control method wherein commands are sent from a host to a target using iSCSI control protocol  
Provided are an information processing apparatus and a command multiplicity control method that enable easy and proper control of command multiplicity assigned to each host. The information...
7689733 Method and apparatus for policy-based direct memory access control  
A computer that operates in a metered mode for normal use and a restricted mode uses an input/output memory management unit (I/O MMU) in conjunction with a security policy to determine which...
7680963 DMA controller configured to process control descriptors and transfer descriptors  
In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The...
7676605 Methods and apparatus for bridging a bus controller  
A method for coordinating descriptor lists updates between a host computer and a client computer, where the host and the client each maintain respective descriptor lists of bus controller commands....
7660910 Secure communication port redirector  
A method and system that allows a host system application to securely communicate with a legacy device is provided. A redirector software module receives data that is destined for a host system...
7657667 Method to provide cache management commands for a DMA controller  
The present invention provides a method and a system for providing cache management commands in a system supporting a DMA mechanism and caches. A DMA mechanism is set up by a processor. Software...
7644206 Command queue ordering by positionally pushing access commands  
A data storage system is provided with command queue controller circuitry for positionally pushing pending access commands from a command queue to a selected target zone of a storage space. A...
7634593 System and method for DMA transfer  
A system for DMA transfer includes a DMA controller, a bus connected to the DMA controller, a bus interface connected to the bus, and a plurality of registers coupled to the bus via the bus...
7631114 Serial communication device  
The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the...
Matches 1 - 50 out of 197 1 2 3 4 >