Matches 51 - 100 out of 157 < 1 2 3 4 >


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6985983 Translating device adapter having a common command set for interfacing multiple types of redundant storage devices to a host processor  
A translating host bus interface adapter is capable of connecting a computer system as a compute node to a storage area network. The adapter has a processor and a memory system containing firmware...
6976107 Adaptive spin latches  
An adaptive spin latch system is provided for use in a multiprocessor computer system. The spin latch system includes a run queue, a spin latch module and a wait queue. The run queue is adapted to...
6961828 Cluster system, memory access control method, and recording medium  
Description of a parallel program is facilitated in a cluster system which loosely couples a plurality of server computers each having a cluster file system. In the cluster system, an application...
6954929 Method for just-in-time updating of programming parts  
The invention provides a method of implementing firmware updates to programmable parts within circuit boards on a manufacturing line. An image file of firmware for each of the parts is created and...
6944681 Probing algorithm for foundation fieldbus protocol  
A hand-held communication control device which, when coupled to a process control system communication bus, controls communication occurring on the bus using a communication schedule that dictates...
6944687 Reducing power consumption of an electronic system having a communication device  
A computer system comprises a host computer coupled to a wireless module via a digital interface. The wireless module permits the computer system to communicate with a wireless network. The host...
6938139 Method and system for data element change across multiple instances of data base cache  
A method and system for updating and maintaining cache coherency across nodes in a cluster. The method uses a combination of read and write locks on the instances of the cache, with some...
6938095 Method and apparatus for establishing and sharing a virtual change notification list among a plurality of peer nodes  
A data structure has a list of event objects, one or more producers creating the event objects for the list, and a finite set of consumers accessing the object list. The structure is characterized...
6912609 Four-phase handshake arbitration  
A four-phase arbitration system employs a master and a slave arbiter. The master arbiter operates to provide ownership of a bus to a first device if a second device, coupled to the slave arbiter...
6865631 Reduction of interrupts in remote procedure calls  
A method and system for executing one or more remote procedure calls. In one embodiment, a method comprises the step of a processing unit issuing a plurality of commands to a corresponding DMA...
6862646 Method and apparatus for eliminating the software generated ready-signal to hardware devices that are not part of the memory coherency domain  
The specification discloses a method and related system that allows hardware devices to participate in the coherency domain of a computer system. More particularly, hardware devices such as...
6851005 Apparatus and method for implementing raid devices in a cluster computer system  
Apparatus and methods are provided for efficiently implementing logical-device reservations in a cluster computer system. The apparatus includes cooperating controllers programmed in firmware...
6842847 Method, apparatus and system for acquiring a plurality of global promotion facilities through execution of an instruction  
A multiprocessor data processing system includes first and second processors coupled to an interconnect and to a global promotion facility containing a plurality of promotion bit fields. The first...
6839811 Semaphore management circuit  
A circuit includes a register which stores therein a semaphore address, and further includes a semaphore control circuit which asserts a control signal in response to a read access by a processor...
6834332 APPARATUS AND METHOD FOR SWAPPING-OUT REAL MEMORY BY INHIBITING I/O OPERATIONS TO A MEMORY REGION AND SETTING A QUIESCENT INDICATOR, RESPONSIVE TO DETERMINING THE CURRENT NUMBER OF OUTSTANDING OPERATIONS  
An apparatus and method for swapping out real memory by inhibiting input/output (I/O) operations to a memory region are provided. The apparatus and method provide a mechanism in which a quiesce...
6829698 Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction  
A data processing system includes a global promotion facility and a plurality of processors coupled by an interconnect. In response to execution of an acquisition instruction by a first processor...
6785756 Methods and systems for multi-policy resource scheduling  
A method of managing an allocation of a plurality of resources of a computer system adapted to support a plurality of processes includes a step of selecting one of a plurality of policy modules to...
6779090 Spinlock for shared memory  
A spin lock for shared memory is disclosed. A lock flag for a lock on a memory section is attempted to be set. If the lock flag is successfully set, the lock on the memory section is held so that...
6757769 Cooperative lock override procedure  
Queued lock services for managing a shared resource in a data processing system include a cooperative lock override procedure. On detecting a protocol failure by another processor, the detecting...
6754752 Multiple memory coherence groups in a single system and method therefor  
A multi-processing system (10) comprises a plurality of groups, each having an arbitrary number of processing systems (11, 12). Memory coherency may or may not be established within any particular...
6748508 Method and apparatus for buffering in multi-node, data distribution architectures  
The present invention provides a method and apparatus for buffering in multi-node data distribution architectures. One embodiment of the present invention groups data items into frames and stores...
6687754 Method of detecting a device in a network  
A method is disclosed for permitting devices connected to a network to identify characteristics of other devices connected to a network. The devices may automatically obtain information about the...
6678773 Bus protocol independent method and structure for managing transaction priority, ordering and deadlocks in a multi-processing system  
A multi-processing system (50) utilizes an interconnect fabric (59) for coupling endpoint devices (52, 54, 56, 66, 67). Bus control functions are managed in a method which is bus protocol...
6671756 KVM switch having a uniprocessor that accomodate multiple users and multiple computers  
A KVM switch having a uniprocessor architecture that accommodate multiple users and multiple computers—even multiple users to a single computer—via interrupt servicing provides dramatic...
6657973 Communications node, network system and method of controlling network system  
In a computer network including plural communications nodes connected through buses, the bus use efficiency in data transfer is improved. A root node having received a transmitted data from a...
6630926 Apparatus and method for verifying keystrokes within a computing system  
A computing system includes a security register, in which a flag bit is set whenever a clock pulse and scan code are transmitted from the microcontroller in the system keyboard. The presence of...
6629220 Method and apparatus for dynamic arbitration between a first queue and a second queue based on a high priority transaction type  
Dynamic arbitration based on a high priority transaction type. A first memory access request is received at a first request queue. If the first memory access request is of a first type, the...
6604160 Computing system arbitrating and selectively providing resource-seeking tasks with takeaway of non-shareable resources  
In a computing system with non-shareable resources, use-arbitrating processes are executed on behalf of each task seeking or having access to non-shareable resource. The processes compete...
6584528 Microprocessor allocating no wait storage of variable capacity to plurality of resources, and memory device therefor  
A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the...
6564258 Detection of network topology changes affecting trail routing consistency  
There is disclosed a method and apparatus for detection of client trails which may become unsupported due to reconfiguration of node elements within a network at a server layer, and a rerouting...
6549881 Interface for interfacing simulation tests written in a high-level programming language to a simulation model  
The present invention is directed to a system having a shared processing resource, a plurality of processing modules and a synchronization control module. The shared processing resource is...
6532510 Computer system for processing system management interrupt requests  
A computer system processes system management interrupt (SMI) requests from plural system management (SM) requesters. Different SM requesters are provided with different priority levels such that...
6529984 Dual phase arbitration on a bus  
A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the...
6499031 Systems and methods for using locks with computer resources  
Provided is a method for locking computer resources and for accessing locked computer resources. Resources being used by remote users can be locked such that other remote users and local users...
6484217 Managing shared devices in a data processing system  
Disclosed is a method and device adapter for managing devices in a data processing system that includes a plurality of device adapters connected for independent communication with at least one...
6484221 Bus extension for multiple masters  
A network bus for interconnecting a plurality of medical devices is described in which the devices are provided with modules adapted to communicate along the bus. Some of the devices are capable...
6477597 Lock architecture for large scale system  
The lock architecture for a computer system comprises several processors (10, 11, 12, 13) such that each processor (10) requesting a resource of the system takes control of said resource if a...
6421751 Detecting a no-tags-free condition in a computer system having multiple outstanding transactions  
A computer system includes a pipelined communication link on which pipelined transactions are identified by a tag. A finite number of tags are available. The computer system detects where all the...
6412034 Transaction-based locking approach  
According to a transaction-based locking approach, a request for a first lock on a particular resource is received from a first process, wherein the first process is associated with a first...
6353869 Adaptive delay of polling frequencies in a distributed system with a queued lock  
A queued lock prioritizes access to a shared resource in a distributed system. Each unsuccessful requestor adaptively delays its next poll for the lock by a period determined as a function of its...
6308274 Least privilege via restricted tokens  
A method and mechanism to enforce reduced access via restricted access tokens. Restricted access tokens are based on an existing token, and have less access than that existing token. A process is...
6253273 Lock mechanism  
A method of providing a lock to a requester, the method including the steps of storing a lock indicator at a storage location on a storage medium; receiving a lock command from a requester on a...
6240476 Dynamic allocation of bus master control lines to peripheral devices  
A computer system includes a system bus, peripheral devices, bus control logic having bus control lines for bus master operation, and an allocation control circuit. The allocation control circuit...
6230198 Server-to-server event logging  
Disclosed are a method, embodiable in computer readable program code, and a system for providing server-to-server event logging. A server-to-server event message is generated including 1) an event...
6216172 Automatic can address allocation method  
For automatic CAN address allocation each bus subscriber still to be allocated an address, generates a random value for a provisional address on system power up. On receiving a request to commence...
6212165 Apparatus for and method of allocating a shared resource among multiple ports  
An apparatus for and a method of collapsing multiple ports to a single queue. The invention has applications in switching devices whereby several external ports share the same resource, such as a...
6182165 Staggered polling of buffer descriptors in a buffer descriptor ring direct memory access system  
A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that polls buffer descriptors when in idle mode. This polling is to determine whether the software has set up...
6173354 Method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus  
A method and apparatus for decoupling internal latencies of a bus bridge from those on an external bus is described. In one embodiment, the method includes detecting a write cycle by an initiator...
6169929 Automatic polling for user interrupts in a programmable controller using relay ladder logic  
A programmable controller includes memory for storing a ladder logic control program having a plurality of ladder logic instruction rungs. Each rung begins with a start of rung (SOR) instruction....
6122692 Method and system for eliminating adjacent address collisions on a pipelined response bus  
Described is an apparatus for eliminating early retrying of PAAM address conflicts on a system bus with multiple processors connected by a non-master processor, by comparing addresses of the...

Matches 51 - 100 out of 157 < 1 2 3 4 >