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7620749 |
Descriptor prefetch mechanism for high latency and out of order DMA device
A DMA device prefetches descriptors into a descriptor prefetch buffer. The size of descriptor prefetch buffer holds an appropriate number of descriptors for a given latency environment. To support...
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7620748 |
Hardware assisted non-volatile memory-to-input/output direct memory access (DMA) transfer
In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps—data is...
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7620747 |
Software based native command queuing
Systems and methods for performing native command queuing according to the protocol specified by Serial ATA II for transferring data between a disk and system memory are described. Native command...
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7620746 |
Functional DMA performing operation on DMA data and writing result of operation
In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read...
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7620745 |
Transferring data between a memory and peripheral units employing direct memory access control
A method transfers data between a memory and peripheral units. The method includes assigning priorities to the data to be transferred, and transferring the data by direct memory access (DMA)...
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7620693 |
System and method for tracking infiniband RDMA read responses
A system and method for tracking responses to InfiniBand RDMA Reads. When an RDMA Read or Read request is issued by a transmit module, a receive module is informed of the packet sequence numbers...
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7617338 |
Memory with combined line and word access
A system for a processor with memory with combined line and word access is presented. A system performs narrow read/write memory accesses and wide read/write memory accesses to the same memory bank...
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7617290 |
Protocol-independent support of remote DMA
A remote DMA (RDMA) shim protocol laid atop an existing network data transfer protocol but logically underneath higher level disk and file access protocols specifies the portion of a data packet to...
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7613876 |
Hybrid multi-tiered caching storage system
A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised...
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7613847 |
Partially virtualizing an I/O device for use by virtual machines
A computer system comprises a physical computer and a virtual machine monitor executable on the physical computer and configured to create an emulation of at least one guest operating system...
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7610433 |
Memory controller interface
A memory interface controller and method to allow a processor designed and configured to operate with NOR flash and static random access memory (SRAM) memory devices to instead operate using NAND...
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7607001 |
Memory management method for simultaneously loading and executing program codes
A method is provided for simultaneously loading and executing program code in a circuit system. The circuit system includes a plurality of memory devices, a microprocessor, and a loading circuit....
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7606961 |
Computer system and data pre-fetching method
A computer system according to an example of the invention comprises SPEs and a global memory. The SPEs include a running SPE and an idling SPE. The running SPE and the idling SPE each have a...
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7606950 |
Graphical programs with direct memory access FIFO for controller/FPGA communications
A system and method for communicating between graphical programs executing on respective devices, e.g., a programmable hardware element and a controller. The system includes a first node...
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7603489 |
Direct memory access controller including first and second transfer setting registers
DMAC includes current transfer setting registers and next transfer setting registers. Each of the current transfer setting registers stores transfer source address, transfer destination address and...
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7603488 |
Systems and methods for efficient memory management
Systems and methods for providing efficient memory allocation, reduced processor intervention and power consumption, and increased memory access bandwidth. One embodiment comprises a system...
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7596644 |
Transmit rate pacing system and method
System and method of a pace engine for governing the different transmission rates tailored for different connections by rate pacing a plurality of queues are described. Roughly described, the pace...
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7596639 |
Skip mask table automated context generation
Skip logic is provided in a storage controller that informs a direct memory access (DMA) context list manager of consecutive ones and zeroes in a skip mask table. The DMA context list manager then...
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7594057 |
Method and system for processing DMA requests
Method and system for processing direct memory access (DMA) requests in a peripheral device is provided. The method includes generating a DMA request to transfer information to/from a host system,...
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7594056 |
Bridge and data processing method therefor
There is provided a bridge which connects between a primary bus and secondary bus. The bridge reads out a descriptor from a primary memory of the primary bus, reads out a status from a secondary...
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7594042 |
Effective caching mechanism with comparator coupled to programmable registers to store plurality of thresholds in order to determine when to throttle memory requests
A system includes a plurality of bus masters that generate direct memory access requests to access a protected memory device. Before granting the access, the system checks for memory protection...
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7590774 |
Method and system for efficient context swapping
Systems and methods for efficiently switching context between processing elements are disclosed. These systems and methods may transfer the context of a processing element to a storage location....
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7587525 |
Power control with standby, wait, idle, and wakeup signals
An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a...
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7587524 |
Camera interface and method using DMA unit to flip or rotate a digital image
A camera interface employing a direct memory access (DMA) unit to digitally perform an image transformation such as “flipping” and “rotating” an image (e.g., to correct for X-axis, Y-axis,...
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7584307 |
Direct memory access DMA with positional information and delay time
An information processor includes: generating section generating a descriptor, the descriptor including positional information, which indicates a packet-by-packet recording position of the data in...
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7581072 |
Method and device for data buffering
A data buffer device that includes a write unit and a read unit, and is disposed between a first interface device and a second interface device is provided. The write unit further includes a first...
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7581039 |
Procedure and device for programming a DMA controller in which a translated physical address is stored in a buffer register of the address processing unit and then applied to the data bus and stored in a register of the DMA controller
A method for programming a DMA controller of a system on a chip that includes a CPU, an MMU, and a DMA controller including source, destination, and size registers associated with a base...
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7577774 |
Independent source read and destination write enhanced DMA
The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to...
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7577773 |
Method and system for DMA optimization
Method and system for processing read requests sent by a network interface device to a host system is provided. The method includes sending staggered read requests within a programmable time...
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7577772 |
Method and system for optimizing DMA channel selection
A host bus adapter coupled to a network and a host computing system is provided. The host bus adapter includes a direct memory access (“DMA”)mode detection module that receives a DMA channel...
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7574536 |
Routing direct memory access requests using doorbell addresses
An infrastructure element can receive a first DMA request including a first address and the data, generate a meta request that comprises a resource key value and a doorbell address, and transmit...
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7571284 |
Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
A method and apparatus for implementing out-of-order memory transactions in a multithreaded, multicore processor. In the present invention, circular queue comprising a plurality of queue buffers is...
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7570646 |
Apparatus and method for an interface unit for data transfer between a host processing unit and a multi-target digital signal processing unit in an asynchronous transfer mode
A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous transfer mode (ATM) of operation. The...
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7568055 |
Data processing apparatus for selecting either a PIO data transfer method or a DMA data transfer method
The image processing apparatus (data processing apparatus) stores data in a storing unit (storing means), inputs and outputs the data to and from the storing unit via a storage control unit...
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7568054 |
Duplicate synchronization system and method of operating duplicate synchronization system
The duplicate synchronization system has: a first system; and a second system operating in synchronization with the first system. The first and the second systems are connected to each other. The...
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7565460 |
Information processing apparatus and method for handling packet streams
A control machine which uses a data amount stored in an FIFO as a trigger and allows a DMA transfer to be started according to a capacity of the FIFO allows a control machine for preparing for the...
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7562165 |
USB host system, AV data reproduction apparatus and AV data recording apparatus
A USB host system includes a USB host controller including a transfer memory for USB data transfer. In the transfer memory, a plurality of transfer descriptor regions are allocated. Transfer...
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7555577 |
Data transfer apparatus with channel controller and transfer controller capable of slave and standalone operation
A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues data transfer requests. The transfer controller...
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7552257 |
Data transmission device with a data transmission channel for the transmission of data between data processing devices
The present invention provides a data processing apparatus having at least one dedicated data processing device ( 10 ) of a first type, a central data processing device ( 4 ) for controlling...
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7552250 |
DMA slot allocation
Methods, systems, and devices are provided for a media platform. One method includes receiving DMA requests for connecting media data traffic to DMA slots of a DMA memory module. Available DMA...
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7552249 |
Direct memory access circuit and disk array device using same
A DMA circuit prevents an erroneous data transfer by a descriptor due to an address failure of memory. When a descriptor is created, the data processing unit writes a pointer, for storing the...
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7552240 |
Method for user space operations for direct I/O between an application instance and an I/O adapter
The present invention provides a method that enables application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from either the local...
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7548997 |
Functional DMA performing operation on DMA data and writing result of operation
In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read...
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7548996 |
Data streamer
In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer...
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7546397 |
Systems and methods for allowing multiple devices to share the same serial lines
Methods and systems for allowing multiple devices to share the same serial lines (e.g., SDIO, SEN and SCLK) are provided. Such devices can be located, e.g., on an optical pick-up unit. Each device...
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7546393 |
System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups
The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter...
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7546392 |
Data transfer with single channel controller controlling plural transfer controllers
A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer...
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7546391 |
Direct memory access channel controller with quick channels, event queue and active channel memory protection
A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes...
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7543290 |
Multiple queue pair access with single doorbell
A method for controlling access by processes running on a host device to a communication network includes assigning to each of the processes a respective doorbell address on a network interface...
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7539790 |
Reducing latency in SCSI protocol
To communicate over a SCSI protocol, a first device allocates buffers for a dummy SCSI read command and sends the dummy SCSI read command to a second device. This dummy SCSI read command is not a...
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