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8185683 |
Bridge, information processing system, and access control method
Transparency of resources is provided and ordering in an access is guaranteed between nodes on a computer network. In an information processing system in which a plurality of processor units are...
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8185672 |
Transmission of data bursts on a constant data rate channel
A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving...
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8180928 |
Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney
Certain embodiments of the invention may be found in a method and system for performing SCSI read operations with a CRC via a TCP offload engine. Aspects of the method may comprise receiving an...
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8176220 |
Processor-bus-connected flash storage nodes with caching to support concurrent DMA accesses from multiple processors
A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash...
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8174368 |
Reading method, responder, and interrogator
Transmission and reception of the identification number to/from an interrogator includes an interrogator that reads a recognition number from a responder by radio. When a clock pulse is modulated...
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8176252 |
DMA address translation scheme and cache with modified scatter gather element including SG list and descriptor tables
A scatter gather element based caching system is provided along with a modified scatter gather element, that supports efficient logical to physical address translation for arbitrarily aligned and...
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8176221 |
DMA controller
A DMA controller achieving real-time control of a DMA transfer relating to periodically operated peripheral devices at a low cost and with low power consumption. A typical embodiment of the...
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8176348 |
Control device and information processing apparatus
A control device includes a main control unit that serves as a main component for device control and to which power is supplied from a first power unit; a power control unit that controls the first...
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8171316 |
Mobile system on chip (SoC) and a mobile terminal including the mobile SoC
A mobile System on Chip (SoC) including a central processing unit (CPU) and an audio out module that includes a buffer and an audio interface. A power mode of the audio out module is controlled...
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8171213 |
Information processing apparatus and method, and program
Disclosed herein is an information processing apparatus, including: setting means for setting, a maximum transfer size; calculation means for subtracting a second data amount from a first data...
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8166212 |
Predictive DMA data transfer
A compression and storage device comprises: a compressor configured to compress data; a central processing unit (CPU) configured to control storage of the compressed data and to perform at least...
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8161206 |
Method and system for storing memory compressed data onto memory compressed disks
In a computer system supporting memory compression and wherein data is stored on a disk in a different compressed format, and wherein an IOA (input/output adaptor)/IOP (input/output processor)...
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8156259 |
Memory data transfer method and system
A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a...
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8156260 |
Data transfer device and method for selecting instructions retained in channel unit based on determined priorities due to the number of waiting commands/instructions
A data transfer device for performing direct memory access (DMA) transfer of data stored in a storage unit to a plurality of other devices includes: a plurality of channel units arranged to...
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8156261 |
Methods and apparatus for providing data transfer control
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing...
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8151008 |
Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling
A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a...
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8151046 |
Disk array apparatus and method for controlling the same
The disk array apparatus includes a controller having a communication control unit for accepting a data input/output request, a disk controller unit for controlling a plurality of disk drives, and...
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8151015 |
Systems and methods for effecting DMA data transfers
Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a...
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8150670 |
Simulator and simulation method
An object of the present invention is to provide a simulator for verifying plural products with common hardware configuration, in which peripheral hardware that can be reused are constituted by...
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8149854 |
Multi-threaded transmit transport engine for storage devices
An embodiment of the present invention is a technique to process a plurality of I/O sequences associated with a storage device. A task context pre-fetch engine pre-fetches a task context from a...
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8151014 |
RAID performance using command descriptor block pointer forwarding technique
The apparatus in one example may have: at first and second processing devices; at least one sequence of processes for the first and second devices; the at least one sequence having a command...
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8145804 |
Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor
A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers...
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8135934 |
Dynamically allocating limited system memory for DMA among multiple adapters
A method, apparatus, and computer program product dynamically allocate limited system memory for direct memory access (DMA) among a plurality of input/output (I/O) adapters in a system partition....
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8135878 |
Method and apparatus for improving throughput on a common bus
A bus scheduling device having a group of direct memory access (“DMA”) engines, a group of target modules (“TM”), a read pending memory, and a bus arbiter is disclosed. A common bus, which is coup...
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8135923 |
Method for protocol enhancement of PCI express using a continue bit
In a method for enabling a root device to access a plurality of memory locations in an address space in an endpoint device, a first access is sent to the endpoint device by transmitting a first...
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8131889 |
Command queue for peripheral component
In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash...
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8127053 |
System and method for peripheral device communications
A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the...
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8127052 |
Data transfer control device and computer system
A data transfer control device includes a control component (DMA controller 5) which acquires a data transfer instruction including, as its parameters, start memory addresses or start input/output...
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8122155 |
RDMA write completion semantics
An RDMA Network Interface Controller (NIC) is operated to accomplish an RDMA WRITE operation initiated by an application operating on a host computing device to which the RDMA NIC is coupled for...
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8122164 |
Information processing apparatus having first DMA controller and second DMA controller wherein selection circuit determines which DMA will perform data transfer based on higher data transfer performance
Provided is an information processing apparatus and method of controlling same in which, when data transfer is performed among a plurality of control circuits, which control circuit is used to...
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8122125 |
Deep packet inspection (DPI) using a DPI core
Illustrated is a system for performing Deep Packet Inspection (DPI) that includes a core to prepare a data packet for transmission. Further, the system includes a memory controller to direct the...
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8117356 |
Direct memory access (DMA) transfer of network interface statistics
In general, in one aspect, the disclosure describes a method that includes maintaining statistics, at a network interface, metering operation of the network interface. The statistics are...
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8117475 |
Direct memory access controller
A system has a central processing unit (CPU) operable to operate in a sleep or low power mode and in an active mode, a plurality of system components operable to operate in a sleep or low power...
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8111721 |
Multiplexing apparatus and method
A multiplexing system (10) is provided which includes a plurality of encoders (12-15) which generates elementary streams, respectively, CPU (16), multiplexer (17), instruction memory (18), and a...
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8112559 |
Increasing available FIFO space to prevent messaging queue deadlocks in a DMA environment
Embodiments of the invention may be used to manage message queues in a parallel computing environment to prevent message queue deadlock. A direct memory access controller of a compute node may...
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8112560 |
Controlling complex non-linear data transfers
A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data...
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8112590 |
Methods and apparatus for reducing command processing latency while maintaining coherence
In a first aspect, a first method of reducing command processing latency while maintaining memory coherence is provided. The first method includes the steps of (1) providing a memory map including...
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8108571 |
Multithreaded DMA controller
A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a...
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8103809 |
Network devices with multiple direct memory access channels and methods thereof
A method, computer readable medium, and a system for communicating with networked clients and servers through a network device includes establishing a plurality of direct memory access (DMA)...
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8103497 |
External interface for event architecture
A device for monitoring events. The device may have a programmable event engine for detecting events and a memory array coupled to the event engine. The array may store data for programming the...
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8099529 |
Software based native command queuing utilizing direct memory access transfer context information
Systems and methods for performing native command queuing according to the protocol specified by Serial ATA II for transferring data between a disk and system memory are described. Native command...
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8099530 |
Data processing apparatus
A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information...
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8099528 |
Data filtering using central DMA mechanism
A method and system is disclosed for passing data processed by a DMA controller through a transmission filter. The method includes the DMA controller accessing data for transfer between an...
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8095616 |
Contention detection
A multiple computer system is disclosed in which n computers (M1, M2 . . . Mn) each run a different portion of a single application program written to execute only on a single computer. The local...
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8095702 |
High speed memory access in an embedded system
Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied...
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8095700 |
Controller and method for statistical allocation of multichannel direct memory access bandwidth
A DMA controller and a method for statistical allocation of multichannel DMA bandwidth. In one embodiment, the DMA controller includes: (1) channel interfaces including respective counters and...
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8095701 |
Computer system and I/O bridge
A computer system reduces an overhead by using an I/O switch high in versatility when realizing the sharing of an I/O between virtual computers. The system includes a CPU module #0 having plural...
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8090790 |
Method and system for splicing remote direct memory access (RDMA) transactions in an RDMA-aware system
Aspects of a system for splicing RDMA transactions in an RDMA system may include a main processor within a main server that may receive read requests from a client device. The main processor may...
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8086765 |
Direct I/O device access by a virtual machine with memory managed using memory disaggregation
Illustrated is a system and method for identifying a memory page that is accessible via a common physical address, the common physical address simultaneously accessed by a hypervisor remapping the...
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8086766 |
Support for non-locking parallel reception of packets belonging to a single memory reception FIFO
A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA...
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