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6865638 |
Apparatus and method for transferring multi-byte words in a fly-by DMA operation
An apparatus and method for transferring multi-byte words having arbitrary start and end byte addresses are described. Data transfers between a memory and a PCI-bus pass through a PCI-side aligner...
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6865631 |
Reduction of interrupts in remote procedure calls
A method and system for executing one or more remote procedure calls. In one embodiment, a method comprises the step of a processing unit issuing a plurality of commands to a corresponding DMA...
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6859848 |
Circuit for controlling sequential access to SDRAM
A DMA controller arbitrates and selects a DMA control information signal received from at least one of a plurality of DMA request blocks and accesses an SDRAM on the basis of the selected DMA...
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6859850 |
Controller for controlling direct memory access
A controller for controlling direct memory access. Such a controller is particularly applicable when applied to a transport interface in the receiver of a digital set-top-box for television...
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6854025 |
DMA scheduling mechanism
A DMA scheduling mechanism for transmission of fragmented buffers having a processor for controlling several devices via a polled interface to interleave DMA data transfers on different...
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6848013 |
Decoding method for reducing delay time
A decoding method for reducing a delay time which makes a decoder perform continuously by controlling a relief width according to the characteristic of an input image is provided. The decoding...
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6848016 |
System and method for efficiently implementing an electronic device architecture
A system and method for efficiently implementing an electronic device architecture preferably includes a primary device that is configured to perform core operating functions in the electronic...
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6848061 |
Drive mechanism control device and method, driving operation confirmation method for a drive mechanism, and programs for implementing the methods
A stepping motor, head, or other drive mechanism is driven with high precision without using a high speed CPU or dedicated hardware. Timing data controlling the timing at which drive mechanism...
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6847180 |
Motor control apparatus and motor control method
Control data is efficiently serially transferred to a drive device for driving a motor without involving the CPU. Data buffers are allocated at specific memory addresses. An address decoder decodes...
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6845409 |
Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices
A switch is presented including a host input/output (I/O) port adapted for coupling to a controller, multiple device I/O ports each adapted for coupling to at least one device, and logic coupled...
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6842791 |
Method and apparatus for memory efficient fast VLAN lookups and inserts in hardware-based packet switches
A technique for decreasing VLAN lookup times in hardware-based packet switches by emulating the functionality of a content addressable memory (CAM) with software and random access memories (RAM)....
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6839347 |
Data transfer controller and electronic device
The objective is to provide a data transfer control device and electronic equipment that are capable of reducing processing overheads, thus enabling high-speed data transfer within a compact...
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6836808 |
Pipelined packet processing
A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed...
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6833728 |
Simultaneous bidirectional signal transmission
A system for simultaneous bi-directional transmission of signals over transmission lines between devices having interface ports includes a first circuit for generating the output signal and a...
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6831916 |
Host-fabric adapter and method of connecting a host system to a channel-based switched fabric in a data network
A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a micro-controller...
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6826634 |
Extended message block for network device drivers
The present invention manages memory buffers in network device drivers in a flexible operating system (e.g., the Solaris operating system) that increase performance of the operating system at high...
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6823403 |
DMA mechanism for high-speed packet bus
A DMA (Direct Memory Access) mechanism is provided that may be of improved performance in particular in connection with high-speed packet buses. A transmit DMA engine for outputting read requests...
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6823437 |
Lazy deregistration protocol for a split socket stack
A method, computer program product, and distributed data processing system for lazy deregistration of memory regions. Specifically, the present invention is directed to memory regions that are...
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6823420 |
Entertainment apparatus
An entertainment apparatus comprising a peripheral device and a controller for controlling the peripheral device. The peripheral device and the controller are connected each other by an address bus...
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6823402 |
Apparatus and method for distribution of signals from a high level data link controller to multiple digital signal processor cores
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the...
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6820187 |
Multiprocessor system and control method thereof
A multiprocessor system including a master processor, a plurality of processor elements, each of which is provided with a local memory, the processor elements being controlled in accordance with...
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6820141 |
System and method of determining the source of a codec
A system and method to determine a port that a codec is attached is disclosed. An access will be attempted to a codec, and the internal hardware of the host will watch which input port the response...
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6816921 |
Micro-controller direct memory access (DMA) operation with adjustable word size transfers and address alignment/incrementing
A micro-controller direct memory access (DMA) unit includes hardware support for single read of the source address at a source word size and but writes to the target address at an independent...
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6816750 |
System-on-a-chip
A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high...
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6816922 |
Digital signal processor with a byte DMA controller
A digital signal processor includes a byte direct memory access (DMA) controller and an external memory controller, both of which are coupled to each other. The external memory controller is...
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6816924 |
System and method for tracing ATM cells and deriving trigger signals
A trace and debug support unit ( 120 ) that works in conjunction with a bus sniffer ( 112 ). The trace and debug support unit ( 120 ) maintains in memory one or more configurable filter rules which...
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6813653 |
Method and apparatus for implementing PCI DMA speculative prefetching in a message passing queue oriented bus system
Speculative prefetching during DMA reads in a message-passing, queue-oriented bus system is controlled by creating a special data structure, called a “DMA scoreboard”, for each work queue entry...
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6813652 |
Reduced-overhead DMA
A plurality of direct memory access data transfers are accomplished to transfer data from a host to an adaptor. For each transfer, an indication of locations of at least one group of storage...
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6810443 |
Optical storage transfer performance
One embodiment involves having a processor write a data transfer command to cacheable system memory. The processor then performs a write transaction to a deliver a “packet” command to an...
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6810442 |
Memory mapping system and method
A debug system generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device for used in electronic design automation (EDA). The FPGA device (Behavior...
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6807587 |
Methods and apparatuses for guaranteed coherency of buffered direct-memory-access data
A method for ensuring data coherency in buffered direct memory access (DMA) data transfers. The DMA controller realizes the last piece of data is being transferred to the write buffer. The DMA...
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6804729 |
Migrating a memory page by modifying a page migration state of a state machine associated with a DMA mapper based on a state notification from an operating system kernel
An atomic memory migration apparatus and method are provided. With the apparatus and method, all active DMA mappings to a given physical page of memory are identified and future mappings/unmappings...
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6804698 |
Data transfer
A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data...
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6801958 |
Method and system for data transfer
According to one embodiment of the present invention, a system ( 10 ) for data transfer is disclosed that comprises a transfer memory ( 24 ) having one or more buffers ( 40, 42, 44, 46 , and 48 )....
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6799200 |
Mechanisms for efficient message passing with copy avoidance in a distributed system
An efficient mechanism for sending messages without the use of intermediate copies (i.e. without the staging of data) is provided. In particular an interface specification which allows use users of...
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6799232 |
Automatic byte swap and alignment for descriptor-based direct memory access data transfers
A physical interface card for connection to a data bus associated with a data network node is provided. The physical interface card is adapted to perform without supervision from other data bus...
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6799227 |
Dynamic configuration of a time division multiplexing port and associated direct memory access controller
An apparatus comprising a transmit data path, a receive data path, a first circuit and a second circuit. The first circuit may be configured to transfer data between a first interface and the...
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6795893 |
Recordable disk recording controller with batch register controller
In a recordable disk recording controller circuit, a data buffer manager receives a command and sends the command to a micro-controller. The micro-controller generates a set of register batches...
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6795874 |
Direct memory accessing
A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data...
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6792506 |
Memory architecture for a high throughput storage processor
A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of...
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6789172 |
Cache and DMA with a global valid bit
A digital system has at least one processor, with an associated multi-segment cache memory circuit. A single global validity circuit (VIG) is connected to the memory circuit and is operable to...
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6789140 |
Data processor and data transfer method
The data processor for processing operation data stored in a memory connected to an external bus in the order of operations includes: an interface section for holding a parameter required for...
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6785745 |
Recording/reproducing device
A recording/playback apparatus includes an upper control unit which transmits a composite command, which includes a real processing command and a virtual command, to a disk device. The disk device...
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6785776 |
DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism
A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system...
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6785775 |
Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues
A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies...
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6785743 |
Template data transfer coprocessor
The template data transfer coprocessor (TDTP) offloads block data transfer operations from a mediaprocessor. A uni-block template, program-guided template, an indirect template and queue-based...
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6785751 |
Method and apparatus for minimizing bus contention for I/O controller write operations
Inform writes to inform a controller of availability of a plurality of replacement data buffers are optimally batched as a single message. Batching the inform writes lets the controller maintain...
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6782465 |
Linked list DMA descriptor architecture
A linked list DMA descriptor includes an indication of a number of data pointers contained in a subsequent DMA descriptor. The number of data pointers contained in the subsequent DMA descriptor is...
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6782456 |
Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism
A method and data processing system that supports pipelining of Input/Output (I/O) DMA Write transactions. An I/O processor's operational protocol is provided with a pair of instructions/commands...
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6782463 |
Shared memory array
Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and...
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