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7107374 |
Method for bus mastering for devices resident in configurable system logic
A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a...
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7103764 |
Parallel port with direct memory access capabilities
The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor...
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7103888 |
Split model driver using a push-push messaging protocol over a channel based network
A channel based network is provided that allows one or more hosts to communicate with one or more remote fabric attached I/O units. A split-model network driver includes a host module driver and...
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7103684 |
Single-chip USB controller reading power-on boot code from integrated flash memory for user storage
A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than...
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7103744 |
Binding a memory window to a queue pair
The disclosed embodiments may relate to memory window access and may include a memory window and plurality of queue pairs associated with a process. Each of the plurality of queue pairs may be...
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7099961 |
System including real-time data communication features
In an embodiment of the invention, a system includes a direct memory access (DMA) engine to move data on a real time basis and a communication front-end to transmit and receive the data. In another...
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7096472 |
Systems and methods for ensuring atomicity of processes in a multitasking computing environment
In the present invention, a computer in which a plurality of programs are executed under a management of an Operation System having a memory management mechanism includes a unit for ensuring...
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7089289 |
Mechanisms for efficient message passing with copy avoidance in a distributed system using advanced network devices
An efficient mechanism for sending messages without the use of intermediate copies (i.e. without the staging of data) is provided. In particular an interface specification which allows use users of...
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7089336 |
Arbitrating and servicing polychronous data requests in Direct Memory Access
Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system...
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7089344 |
Integrated processor platform supporting wireless handheld multi-media devices
A direct memory access system consists of a direct memory access controller establishing a direct memory access data channel and including a first interface for coupling to a memory. A second...
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7085858 |
Configuration in a configurable system on a chip
The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The...
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7082482 |
Data handling device
A data handling device comprising a communication controller, having a data gate provided for receiving and transmitting data, said communication controller being connected to a processor having an...
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7080162 |
Reduced hardware network adapter and communication method
The present invention provides a network interface adapter for connecting a client computer to a computer network that includes a reduced hardware media access controller (MAC) coupled through a...
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7076578 |
Race free data transfer algorithm using hardware based polling
A method and apparatus for a race free data transfer algorithm using hardware based polling. One disclosed method transfers information between a target device and a buffer which is one of a set of...
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7072996 |
System and method of transferring data between a processing engine and a plurality of bus types using an arbiter
A flexible input/output (I/O) interface allows a processing core to communicate high-speed data with a several different types of interfaces including a Direct Memory Access (DMA) interface and a...
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7073087 |
Transition signal control unit and DMA controller and transition signal control processor using transition signal control unit
Transition signal control for creating asynchronous timing is provided using a transition signal control circuit, which includes Muller C elements each with an inverter. The control device is...
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7073007 |
Interrupt efficiency across expansion busses
A method of processing interrupts is described as well as processing devices. A processing device detects an indicator associated with an interrupt signal from an expansion device and transfers...
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7069348 |
System and method for data transmission using PIO accelerator device in an IDE controller
A system and method for upgrading data transmission performance under programmed input/output (PIO) mode is disclosed. In one embodiment, a PIO accelerating device is established in an IDE...
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7069350 |
Data transfer control system, electronic instrument, and data transfer control method
A data transfer control system receives a command packet ORB (SBP-2) transferred through a bus BUS 1 (IEEE1394), and issues a command included in the ORB to a device connected with a bus BUS 2 ...
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7062591 |
Controller data sharing using a modular DMA architecture
A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller...
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7058735 |
Method and apparatus for local and distributed data memory access (“DMA”) control
An apparatus for local direct memory access control includes a processor unit for generating a direct memory access designator when needed data is not available and continuing processing which does...
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7054986 |
Programmable CPU/interface buffer structure using dual port RAM
Disclosed is a programmable buffer circuit ( 16 ) for interfacing a CPU ( 12 ) to a plurality of channel interfaces ( 14 ). The buffer circuit includes a dual port memory ( 18 ) having a first port...
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7054958 |
Apparatus and method for responding to a interruption of a packet flow to a high level data link controller in a signal processing system
In a data processing system including a plurality of digital signal processor subsystems, selected peripheral components are shared by the digital signal processor subsystems. In particular, the...
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7054985 |
Multiple hardware partitions under one input/output hub
A method and a mechanism are capable of partitioning computer hardware components or elements at the level of individual processing paths, or ropes. Incoming and outgoing queues may be designed...
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7054959 |
Isochronous data transfer control method including packet configuration of thus-read isochronous header and data
A processing section reserves a number of transfers for an isochronous packet which includes isochronous data in an transfer number reservation register TNREG. A DMAC 1 reads that isochronous...
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7051123 |
Data transfer engine of a processor having a plurality of modules
In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer...
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7046686 |
Integrated circuit that processes communication packets with a buffer management engine having a pointer cache
An integrated circuit processes communication packets and comprises a pointer cache and control logic. The pointer cache store pointers that correspond to external buffers that are external to the...
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7039779 |
Access monitor and access monitoring method for monitoring access between programs
An access violation of the program is monitored by the access monitor which is a hardware. The access monitor acquires a signal input from the CPU to a memory. The access monitor includes an access...
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7035908 |
Method for multiprocessor communication within a shared memory architecture
An apparatus comprising a shared memory and a multiprocessor logic circuit. The shared memory may be configured to store data. The multiprocessor logic circuit may comprise a plurality of...
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7032226 |
Methods and apparatus for managing a buffer of events in the background
A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a...
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7028123 |
Microcomputer, has selection circuit to select either testing-purpose interrupt request signal or interrupt request selection signal based on delayed selection signal, where selected signals are sent to interrupt controller
In a microcomputer, a testing-purpose interrupt request signal generator generates a testing-purpose interrupt request signal, an interrupt request selecting register stores an interrupt request...
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7024495 |
Programmable controller
A programmable controller has a multi-purpose processor such as an MPU and an application specific control device such as an ASIC (application specific integrated circuit). When the MPU requests...
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7020724 |
Enhanced power reduction capabilities for streaming direct memory access engine
A streaming direct memory access (DMA) engine is disclosed. The streaming DMA engine includes several power reduction capabilities. A controller throttles the DMA engine according to the system...
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7016942 |
Dynamic hosting
For client/server network connectivity, clients connect to a server at a predesignated address. With client/server connectivity, if client-to-client communication is required, even for extended...
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7016213 |
Method for initializing a system including a host and plurality of memory modules connected via a serial memory interconnect
A host is coupled to a serially connected chain of memory modules. In one embodiment, a method for initializing the host and each of memory modules includes the host transmitting a first...
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7016987 |
Transaction aligner microarchitecture
A computer system is provided that includes a direct memory access (DMA) controller, a memory control device and a slave device, all coupled to a system bus. The DMA controller is configured to...
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7010711 |
Method and apparatus of automatic power management control for native command queuing Serial ATA device
The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active...
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7010626 |
DMA prefetch
A method and an apparatus are provided for prefetching data from a system memory to a cache for a direct memory access (DMA) mechanism in a computer system. A DMA mechanism is set up for a...
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7000244 |
Multi-threaded direct memory access engine for broadcast data demultiplex operations
A method and system for transferring a transport stream, such as from a satellite receiver to a networked computer system, are provided. The transport stream is parsed to derive multiple elementary...
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6996655 |
Efficient peer-to-peer DMA
Peer-to-peer Direct Memory Access (DMA) permits the efficient transfer of data from one DMA capable Application Specific Integrated Circuit (ASIC) block to another without accessing memory. The...
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6985977 |
System and method for transferring data over a communication medium using double-buffering
System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a...
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6985972 |
Dynamic cache coherency snooper presence with variable snoop latency
A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus...
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6986020 |
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
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6981074 |
Descriptor-based load balancing
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently...
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6981072 |
Memory management in multiprocessor system
A system and a method are provided for improving memory management in a multiprocessor system. A direct memory access (DMA) operation is set up for a first processor. A DMA effective address is...
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6976098 |
Arbitrating and servicing polychronous data requests in direct memory access
Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates, the data requests from the system...
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6970978 |
System and method for providing a pre-fetch memory controller
A system and method is disclosed for providing a pre-fetch memory controller in a computer system that comprises a plurality of master agents. The memory controller comprises a bus interface, a...
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6968400 |
Local memory with indicator bits to support concurrent DMA and CPU access
A digital system is provided having at least one processor with an associated multi-segment local memory circuit. Validity circuitry is operable to indicate if each segment of the plurality of...
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6963946 |
Descriptor management systems and methods for transferring data between a host and a peripheral
An improved descriptor system is provided in which read pointers indicate to a host and a peripheral the next location to read from a queue of descriptors, and write pointers indicate the next...
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6963962 |
Memory system for supporting multiple parallel accesses at very high frequencies
A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a...
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