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7191257 |
System and method for real-time processing of nondeterministic captured data events
A system and method for real-time processing of nondeterministic captured data events. The system includes data capture logic configured to capture data events from a nondeterministic data bus; a...
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7188199 |
DMA controller that restricts ADC from memory without interrupting generation of digital words when CPU accesses memory
DMA controller for mixed signal device. A mixed signal integrated circuit with memory control is disclosed. A data conversion circuit is provided that is operable to receive an analog input signal...
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7188197 |
Data transferring apparatus for transferring liquid ejection data and a liquid ejecting apparatus
A data transferring apparatus for transferring liquid ejection data has a decoding unit having a decode circuit, which can perform hardware development on liquid ejection data, a line buffer for...
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7188196 |
Method and apparatus for playing analog audio to multiple codec outputs
Method and apparatus for playing analog audio in an electronic audio system having multiple audio codecs, only one of which has a direct hardware connection to the analog audio source. First analog...
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7185120 |
Apparatus for period promotion avoidance for hubs
A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction...
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7184378 |
Storage system and controlling method thereof, and device and recording medium in storage system
A first storage device control device stores, when a first data write/read request is received, correspondences between first logical units and second logical units referenced when determining...
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7185143 |
SAN/NAS integrated storage system
In a storage system directly connected to a network, if conventional interfaces and protocols are used when an I/O command issued from a file server is transmitted to the storage system, the...
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7177988 |
Method and system for synchronizing processor and DMA using ownership flags
Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module...
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7174395 |
Communication interface method and device utilizing direct memory access data transfer
In asynchronous communication, an efficient data transfer can be performed between an external bus and an internal bus. A packet obtained from the external bus by the asynchronous communication is...
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7174442 |
Data addressing
A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential...
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7171526 |
Memory controller useable in a data processing system
One embodiment relates to a memory controller using an independent memory controller bus in order to transfer data between two or more memories. One embodiment of a data processing system includes...
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7167932 |
System and method for DMA data transferring apparatus and liquid ejection apparatus
Compressed recording data is DMA-transferred to a receiving buffer unit via a system bus one word each. It is DMA-transferred from the receiving buffer unit to a DECU via the system bus. It is...
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7165125 |
Buffer sharing in host controller
A storage device host controller such as an SATA (Serial ATA) host controller and a corresponding method are provided for performing host-to-device and device-to-host communications in a PIO...
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7165126 |
Direct memory access device
A direct memory access device is provided which includes: a designation unit for designating transfer modes, when receiving an instruction to transfer data, to perform byte transfers or word...
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7162564 |
Configurable multi-port multi-protocol network interface to support packet processing
A network interface between an internal bus and an external bus architecture having one or more external buses includes an external interface engine and an internal interface. The external...
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7159048 |
Direct memory access (DMA) transfer buffer processor
A DMA (Direct Memory Access) Exchange Block (DXB) processor may include a receive processor for writing data from a local memory to a host memory over a bus, e.g., a Peripheral Component...
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7155379 |
Simulation of a PCI device's memory-mapped I/O registers
A component, system and method for simulation of a PCI device's memory-mapped I/O register(s) are provided. The PCI simulation component has an initialization component, a configuration space...
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7155541 |
Tables with direct memory access descriptor lists for distributed direct memory access
A direct memory access (DMA) descriptor table to control DMA of information in a memory is disclosed. The DMA descriptor table includes one or more DMA descriptor lists stored in the memory. Each...
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7155722 |
System and method for process load balancing in a multi-processor environment
A load balancing mechanism and technique that monitors a memory interface associated with a processor resource in a processor pool associated with at least one node of a computer network. The...
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7149823 |
System and method for direct memory access from host without processor intervention wherein automatic access to memory during host start up does not occur
A method and system for allowing a host device (e.g., server) to perform programmed direct accesses to peripheral memory (e.g., flash) located on a peripheral device (e.g., HBA), without the...
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7146440 |
DMA acknowledge signal for an IDE device
A method for using a personal computer memory card international association (PCMCIA) controller to communicate with an Integrated Drive Electronics (IDE) drive which includes performing a transfer...
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7143206 |
Method for controlling data transfer unit having channel control unit, storage device control unit, and DMA processor
Embodiments of the invention relate to systems and methods for controlling data transfer. In one embodiment, a method for controlling data transfer comprises receiving a data transfer request from...
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7143211 |
Memory configuration with I/O support
The invention relates to a method for configuring a memory with I/O support. The aim of the invention is to guarantee the processor and I/O functional units that function in time-critical...
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7143247 |
Method and apparatus for parallel execution pipeline data storage in a computer memory
A computer system having a plurality of parallel execution pipelines which may generate data for storing in a memory, data from the pipelines may be stored in a queue prior to accessing the memory...
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7143205 |
DMA controller having a trace buffer
A DMA controller comprises an arbitration unit for arbitrating among a plurality of channels so as to select a DMA request from among a plurality of DMA requests accepted by way of the plurality of...
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7139848 |
DMA protocol extension for packet-based transfer
According to one embodiment a system is described. The system includes a direct memory access (DMA) controller and an input/output (I/O) device coupled to the DMA controller. The DMA controller is...
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7139849 |
Semiconductor integrated circuit device
A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and...
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7136943 |
Method and apparatus for managing context switches using a context switch history table
A method, apparatus and computer instructions for storing data relating to the switch in a context switch history containing a number of prior context switches occurring prior to a current context....
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7133940 |
Network interface device employing a DMA command queue
A network interface device couples a host computer to a network. The network interface device includes a processor and a DMA controller. The processor causes the DMA controller to perform multiple...
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7133902 |
Transmitting acknowledgements using direct memory access
Direct memory accessed is used to perform database operations between two or more machines. Data is read from a first buffer located on a first machine. The data was written into the first buffer...
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7130933 |
Method, system, and program for handling input/output commands
Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device...
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7130934 |
Methods and apparatus for providing data transfer control
A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing...
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7130932 |
Method and apparatus for increasing the performance of communications between a host processor and a SATA or ATA device
A method and apparatus for increasing the performance of communications between a host processor and an interconnected device is provided. The present invention allows data transfers to be...
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7130942 |
Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding
A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor...
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7127563 |
Shared memory architecture
A wireless communications architecture having first and second synchronous memory devices coupled to a virtual channel memory controller by corresponding first and second data buses, and a shared...
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7126715 |
Ink jet recording apparatus and control method therefor
A recording apparatus for recording with use of a recording head having two nozzle arrays arranged side-by-side includes first, second, and third direct memory access (DMA) units, a data converter...
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7124231 |
Split transaction reordering circuit
The present invention provides a technique for ordering responses received over a split transaction bus, such as a HyperTransport bus (HPT). When multiple non-posted requests are sequentially...
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7124211 |
System and method for explicit communication of messages between processes running on different nodes in a clustered multiprocessor system
Embodiments of the invention include a mechanism for explicit communication in a clustered multiprocessor system that supports low-latency, protected, user-mode, communication across the machine...
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7120764 |
Method and related apparatus for controlling data transmission in a memory
A computer system has a processor, a memory for storing data, and a memory controller electrically connected to the processor and the memory for controlling data transmission with the memory. The...
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7120708 |
Readdressable virtual DMA control and status registers
Apparatus and method for carrying out a DMA transfer wherein an address is written into a DMA register of a DMA controller specifying a memory location within a memory device at which either the...
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7120761 |
Multi-port memory based on DRAM core
A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum...
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7116812 |
Method and apparatus for providing a standard video interface
An imaging system and method includes a detector framing node (DFN) being programmable to receive image data from a panel detector, and to store the image data for later transfer of the image data...
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7114016 |
Page-aware descriptor management
A method and apparatus to provide network buffer descriptors grouped by memory page into page groups and access a list of the page groups to manage the allocation and de-allocation of the network...
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7114014 |
Method and system for data movement in data storage systems employing parcel-based data mapping
Embodiments of the present invention provide methods and systems for data movement in data storage systems. For one embodiment, a physical data storage parcel containing a first type of data...
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7111134 |
Subsystem and subsystem processing method
A subsystem and a subsystem processing method are disclosed in which a storage control unit 2000 interposed between a plurality of disk units 3000 and a host computer 1000 has a nonvolatile...
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7111092 |
Buffer management technique for a hypertransport data path protocol
A buffer-management technique efficiently manages a set of data buffers accessible to first and second devices interconnected by a split transaction bus, such as a Hyper-Transport (HPT) bus. To...
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7110437 |
Wireless communications systems and methods for direct memory access and buffering of digital signals for multiple user detection
The invention provides methods and apparatus for multiple user detection (MUD) processing that have application, for example, in improving the capacity CDMA and other wireless base stations. One...
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7107382 |
Virtual peripheral component interconnect multiple-function device
A peripheral component interconnect (PCI) device comprising a bus interface coupled to a component interconnect bus, a plurality of configuration space register sets, and virtual multiple-function...
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7107362 |
Integrated circuit with configuration based on parameter measurement
Embodiments of the present invention provide an integrated circuit. In one embodiment, the integrated circuit comprises logic blocks, a measurement circuit and a control circuit. The measurement...
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7107364 |
Control chip for optical disk drive and method for updating firmware in the control chip
A control chip for updating firmware in an optical disk drive by hardware. The control chip includes a microprocessor for controlling actions of the optical disk drive, a decoder controlled by the...
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