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6782433 Data transfer apparatus  
There is provided a data transfer apparatus for transferring data from a main memory coupled to a main bus to a local memory coupled to a local bus. The data transfer apparatus includes: a...
6779049 Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism  
A method and system for attached processing units accessing a shared memory in an SMP system. In one embodiment, a system comprises a shared memory. The system further comprises a plurality of...
6778930 System for reducing distortion of signals transmitted over a bus  
A computer system measures bus signal distortion and then adjusts certain characteristics of the signal transmitted over the bus, or adjusts other characteristics of the bus or the load on the bus...
6775717 Method and apparatus for reducing latency due to set up time between DMA transfers  
A method and apparatus for reducing latency due to set up time between DMA transfers are described. The method comprises initiating arbitration of DMA channel requests prior to completion of a...
6775716 High-performance DMA controller  
A high-performance DMA controller for controlling data transfer between a main storage means holding various kinds of data and a plurality of local storage means, comprises: an interface for...
6772237 Host controller interface descriptor fetching unit  
The present invention relates to a method and circuit for prefetching direct memory access descriptors from memory of a computer system, and storing the prefetched direct memory access descriptors...
6772238 Parallel port with direct memory access capabilities  
The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor...
6766383 Packet-based direct memory access  
Packet-Based Direct Memory Access. The present invention overcomes the oftentimes hardware consumptive and complex implementation of conventional direct memory access (DMA) that employs...
6766448 Microcomputer for transferring program data to an internal memory from an external memory connected via a bus and a method therefor  
It is to provide a method of transferring a program to an internal memory from an external memory at a high speed and at a high efficiency. The external memory has program data to be transferred...
6763401 Direct memory access controller  
A transfer destination address generator includes an arithmetic device that calculates a difference between a transfer destination address and a transfer source address, a difference holding...
6760789 Microcomputer having temporary storage for received data and method of processing received data  
A first receiving message is stored in a message box and a CPU reads the first receiving message from the message box. Meanwhile, a second receiving message is once stored in the message box and...
6760790 Direct access controller  
A direct memory access controller for transferring data from a transfer source memory region to a transfer destination memory region, comprises: a transfer source address calculation unit which has...
6757776 Control transaction handling in a device controller  
Embodiments of the invention prevent data from being mishandled at a connected device using a system that verifies that data received after receiving a setup command portion of a control...
6754828 Algorithm for non-volatile memory updates  
A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor...
6754785 Switched multi-channel network interfaces and real-time streaming backup  
A memory system ( 100 ) and method of operating the same for storing, manipulating, processing, and transferring data in a data network ( 120 ). Generally, the memory system ( 100 ) includes one or...
6754779 SDRAM read prefetch from multiple master devices  
Improved performance for data read operation is achieved in a read buffer that receives and stores requested information in response to read requests from multiple requesting master devices. A full...
6754733 Shared memory architecture for increased bandwidth in a printer controller  
A printer controller for processing print data includes a data processor, direct memory access controller, first and second memories with corresponding first and second transfer data busses. A bus...
6754724 Kernel creator for creating kernel capable of executing entertainment processing using a peripheral device  
An entertainment apparatus includes a storage unit that stores outside a kernel a device driver for a peripheral device. To make the peripheral device operable, a CPU causes an I/O processor to...
6754732 System and method for efficient data transfer management  
A system and method are disclosed which utilize an enhanced direct memory access (DMA) to both perform a desired data transfer and update data queue directories as needed to properly reflect such...
6754735 Single descriptor scatter gather data transfer to or from a host processor  
A processing system includes a processing device and a host processor operatively coupled to the processing device via a system bus, and implements a scatter gather data transfer technique. The...
6748463 Information processor with snoop suppressing function, memory controller, and direct memory access processing method  
An information processing apparatus with a hierarchized bus structure having a system bus connected to central processing units and cache memories and an I/O bus connected to I/O devices. In...
6745310 Real time local and remote management of data files and directories and method of operating the same  
A memory system ( 100 ) and method of operating the same to provide real-time local and remote management of the memory system are described. Generally, the memory system ( 100 ) includes a memory...
6745264 Method and apparatus for configuring an interface controller wherein ping pong FIFO segments stores isochronous data and a single circular FIFO stores non-isochronous data  
Hardware Description Language (HDL) code is created for an interface controller so that logic requiring device-specific configuration refers to a parameter file. This set of parameters lets...
6742056 Semiconductor device and method for initializing interface card using serial EEPROM  
A semiconductor device for initializing an interface card using a serial EEPROM and an initializing method allow for more effective use of a serial EEPROM used to store the initialization...
6738837 Digital system with split transaction memory access  
A digital system having a split transaction memory access. The digital system can access data from a system memory through a read buffer (FIFO) located between the processor of the digital system...
6738836 Scalable efficient I/O port protocol  
A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of...
6735662 Method and apparatus for improving bus efficiency given an array of frames to transmit  
A single completion status write back is generated by a controller to inform a driver of completion of a transmission of all frames of an array of frames, as opposed to generating individual write...
6735642 DMA doorbell  
A method of direct memory access (DMA) includes receiving a first notification at a DMA engine that a first list of descriptors has been prepared, each of the descriptors in the list including an...
6735645 System and method to eliminate race conditions in input/output operations for high bandwidth architectures  
The present invention is directed to a system and method for eliminating race conditions in RAID controllers while utilizing a high bandwidth internal architecture for data flow. A remote memory...
6735643 Electronic card with dynamic memory allocation management  
An electronic card with dynamic memory allocation management is provided, which requires only one single memory by utilizing a dynamic memory controller having a selector and a first, a second and...
6735639 Direct memory access transfer control circuit  
DMA transfer request signals corresponding to respective channels are received and held in respective transfer request holding circuits. DMA transfers are assigned to the DMA transfer request...
6732198 Methods and apparatus for saving and restoring scatter/gather list processing context in intelligent controllers  
A circuit and associated methods of operation for a standardized scatter/gather list processor component within DMACs and intelligent IOPs. The standardized circuit architecture and methods provide...
6732243 Data mirroring using shared buses  
A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller...
6728796 Arrangement and method for signal processing and storing  
A method is described for storing and processing/filtering signals, as well as a memory arrangement, a signal processing arrangement and, in particular, a digital filter arrangement having a...
6728795 DMA channel for high-speed asynchronous data transfer  
An apparatus and method for transferring high speed asynchronous data using a DMA controller. By using a conventional Universal Serial Asynchronous Receiver Transmitter (USART) with a small buffer,...
6728797 DMA controller  
A DMA controller has a cycle register in which the number of data transfer cycles to be performed in response to a single DMA transfer request is set, a cycle counter for counting the number of...
6728853 Method of processing data utilizing queue entry  
A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which...
6724759 System, method and article of manufacture for transferring a packet from a port controller to a switch fabric in a switch fabric chipset system  
A system, method and article of manufacture are provided for transferring a packet from a port controller to a switch fabric in a switch fabric system. Notification is received indicating that a...
6725292 Direct memory access controller for circular buffers  
A method of transferring a block of data from a first to a second circular buffer of a computer system. The method comprises notifying the DMA controller of the source and destination addresses for...
6721826 Buffer partitioning for managing multiple data streams  
The present invention is directed to a buffer partitioning system and a method employing the system to dynamically partition buffer resources among multiple data streams. The buffer partitioning...
6721820 Method for improving performance of a flash-based storage system using specialized flash controllers  
A system and method for increasing the performance of a flash-based storage system, using specialized flash memory controller(s). Several methods of performance improvement are suggested such as...
6718405 Hardware chain pull  
A controller generally comprising a DMA engine, a processor, and a circuit. The DMA engine may be configured to copy from a system memory to a local memory. The processor may be configured to...
6715004 Method and apparatus for intermediate validation of data transferred between a host and a device  
According to one aspect of the present invention, a method is provided in which a device, in response to a read request issued by a host, transfers data to the host through a series of direct...
6711650 Method and apparatus for accelerating input/output processing using cache injections  
A method for accelerating input/output operations within a data processing system is disclosed. Initially, a determination is initially made in a cache controller as to whether or not a bus...
6708234 Data processing apparatus and DMA data transfer method  
In a data processing apparatus, an image memory has a descriptor region and an image region, the image region storing a plurality of blocks of image data, the descriptor region storing a...
6708233 Method and apparatus for direct buffering of a stream of variable-length data  
A method and apparatus for directly creating a buffer of contiguous payload data from an incoming variable-length data stream utilizes a host controller for providing direct memory access (DMA) to...
6701405 DMA handshake protocol  
A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central...
6701395 Analog-to-digital converter that preseeds memory with channel identifier data and makes conversions at fixed rate with direct memory access  
An integrated circuit including a DMA controller, an ADC having a plurality of conversion channels and address and data ports for connection to external memory means, the DMA controller being...
6701387 Adaptive data fetch prediction algorithm  
A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device...
6701388 Apparatus and method for the exchange of signal groups between a plurality of components in a digital signal processor having a direct memory access controller  
As the digital signal processor has become more flexible, the direct memory access controller has assumed greater computational power to permit the core processing unit to perform its specialized...
Matches 451 - 500 out of 1085 < 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >