Matches 1 - 50 out of 91 1 2 >
Match Document Document Title
7587717 Dynamic master/slave configuration for multiple expansion modules  
A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes...
7523237 Method and protocol for diagnostics or arbitrarily complex networks of devices  
The present invention includes a network having a plurality of communication buses, at least two of the plurality of buses utilizing different communication bus protocols; a plurality of computer...
7512729 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency  
A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes...
7512723 Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system  
A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second...
7502881 Data packet routing mechanism utilizing the transaction ID tag field  
A data packet routing mechanism including a plurality of clients for issuing read requests to a host device, the read requests each including a TAG field for identifying which of the plurality of...
7478183 Method and system for n dimension arbitration algorithm—scalable to any number of end points  
A method, a system and a computer programmable product have been provided for arbitrating bus cycles among a plurality of device nodes. Requests for bus grant are received from the device nodes....
7469308 Hierarchical bus structure and memory access protocol for multiprocessor systems  
A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus...
7460061 Distributed radar data processing system  
A distributed radar data processing system for generating data to be supplied to air traffic control by processing radar data obtained from a radar device, comprises a plurality of data buses...
7447817 Method and system for processing arbitration requests  
Method and system for arbitrating between plural arbitration requests is provided. The system includes a plurality of first stage arbiters that receive plural arbitration requests and a signal that...
7412551 Methods and apparatus for supporting programmable burst management schemes on pipelined buses  
Methods and apparatus for supporting programmable burst management schemes on pipelined buses. The apparatus includes a plurality of bus masters (masters), configured in a plurality of clusters,...
7383363 Method and apparatus for interval DMA transfer access  
A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from...
7360002 Method of arbitrating access to a data bus  
A method for arbitrating access to a data bus among subscribers or bus devices (Tn 1 ,Tn 2 , . . . ), wherein the bus devices are coupled by at least one arbitration ring ( 12; 38, 40, 42, 44,...
7337251 Information processing device with priority-based bus arbitration  
The information processing device comprises first and second master circuits and an arbiter for arbitrating access rights to a bus to which the master circuits are connected. The arbiter has...
7305507 Multi-stage round robin arbitration system  
Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is...
7302510 Fair hierarchical arbiter  
A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to...
7200699 Scalable, two-stage round robin arbiter with re-circulation and bounded latency  
A scalable, two-stage round-robin arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a...
7167939 Asynchronous system bus adapter for a computer system having a hierarchical bus structure  
A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system...
7165133 Multiprocessor system having shared buses, prioritized arbitration, and clock synchronization circuitry  
A multiprocessor system having a plurality of processor elements each of which obtains right to use bus of a first or second shared bus in response to a transfer request for control system data or...
7149828 Bus arbitration apparatus and bus arbitration method  
The present invention is to provide a bus arbitration apparatus and a bus arbitration method not reducing data transfer capability as a whole and preventing a loss of transferred data. It performs...
7127539 Statistic method for arbitration  
A statistic method for arbitration is provided, implementing in an arbitration system comprising a bus, a main controller connected to the bus, and a plurality of peripheral devices able to be...
7024505 Fair arbitration method in a distributed arbitration system  
A method of communicating between an initial device and a target device connected by a plurality of intermediate segments in a distributed arbitration system is provided. The method includes...
7007123 Binary tree arbitration system and method using embedded logic structure for controlling flag direction in multi-level arbiter node  
A binary-tree-based arbitration system and methodology with attributes that approximate a Generalized Processor Sharing (GPS) scheme for rendering fairer service grants in an environment having a...
6954812 Two-stage round robin arbitration system  
Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is...
6950892 Method and system for managing distributed arbitration for multicycle data transfer requests  
A method and system for managing distributed arbitration for multi-cycle data transfer requests provides improved performance in a processing system. A multi-cycle request indicator is provided to...
6912597 Peripheral, peripheral control method, peripheral control system, memory medium for storing peripheral control program, and peripheral control program product  
An object of the present invention is to provide a multi-function peripheral which is easy for a user to operate. To achieve the object, according to the present invention, there is provided a...
6877055 Method and apparatus for efficiently broadcasting transactions between a first address repeater and a second address repeater  
A computer system including a first repeater and a second repeater that is coupled to the first repeater. The computer system also includes a third repeater that is coupled to the first repeater....
6741096 Structure and methods for measurement of arbitration performance  
Circuits and associated methods for operation thereof for gathering real-time statistical information regarding operation of the arbiter circuit in a particular system application. The real-time...
6721833 Arbitration of control chipsets in bus transaction  
A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second...
6678771 Method of adjusting an access sequencing scheme for a number of PCI- compliant units coupled to a PCI bus system  
A method of adjusting an access sequencing scheme for a number of PCI (Peripheral Component Interconnect) compliant units coupled to a PCI bus system on a computer system. These PCI-compliant units...
6625678 Livelock avoidance method  
When a high-level bus converter receives a normal request from any one of a plurality of intermediate-level bus converters, the high-level bus converter converts the normal request into a retry...
6618777 Method and apparatus for communicating between multiple functional units in a computer environment  
A CPU includes a number of functional units that cooperate together to execute instructions. On-chip memory is divided into several sections, each of which is connected to an associated internal...
6542953 Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers  
A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write...
6519666 Arbitration scheme for optimal performance  
A shared bus arbitration scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and resources, some resources having higher priority than...
6457150 Method and apparatus for on-chip monitoring of integrated circuits with a distributed system  
An on-chip monitoring circuit is composed of a plurality of individually addressable nodes that are connected together in a circuit which extends from an external data port to each of the monitored...
6446151 Programmable time slot interface bus arbiter  
A method and apparatus allowing two independent arbiters which do not directly talk to one another to function on a common system bus, allowing efficient operation of a master controller, and...
6411218 Priority-encoding device selection using variable arbitrary rankings  
In the context of a bus-mastering system, a device selector selects the device to control the bus by assigning “combined” priority values to the devices and selecting the device with the...
6385678 Method and apparatus for bus arbitration with weighted bandwidth allocation  
A method and apparatus for bus arbitration wherein each bus agent is assigned a weight that governs the percentage of bandwidth allocated to the agent. In addition, each bus agent may also raise...
6349351 Apparatus and method for data transfer including table that stores relative position of devices and data transfer efficiencies of respective transfer paths  
The invention prevents data transfer in a computer network from being sent via a path incapable of transfer or of poor data transfer efficiency. A central processing unit, a main memory unit, and...
6324609 Method and apparatus providing an improved PCI bus system  
A PCI-to-PCI bridge having a processor configured for performing various routing mode operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing...
6311249 Bus arbitration system having both round robin and daisy chain arbiters  
A bus arbitration system includes a first priority grant signal determination part for primarily determining a priority grant signal among two groups including a plurality of priority request...
6275888 Method for configuring peer-to-peer bus bridges in a computer system using shadow configuration registers  
A method of configuring a computer system having a processor coupled by a host bus to first and second bus devices causes the processor to transmit on the host bus one or more configuration write...
6223236 Hierarchical bus structure data processing apparatus and method with reduced data transfer volume  
A data processing apparatus with a hierarchical bus for realizing appropriate data transfer speed and data processing speed, even if more I/O devices are connected to the data processing apparatus....
6154801 Verification strategy using external behavior modeling  
A verification system and method for verifying operation of an HDL (Hardware Description Language) design of a computer system component are disclosed. The computer system is configured to...
6145042 Timing protocol for a data storage system  
A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes a bus...
6141715 Method and system for avoiding live lock conditions on a computer bus by insuring that the first retired bus master is the first to resubmit its retried transaction  
A computer system avoids livelock conditions on a computer bus coupled to plural bus masters. In response to receiving a transaction request from a first bus master across the computer bus, a bus...
6076128 Data transfer method between buses, bridge devices for interconnecting buses, and data processing system including multiple buses  
The object of the present invention is to eliminate, in a data processing system having multiple buses, a combination of devices that can not be accessed via a PCI to PCI bridge. When an access...
6052738 Method and apparatus in a packet routing switch for controlling access at different data rates to a shared memory  
A method and apparatus for controlling access to a shared memory in a network system is described. The apparatus includes at least one fast port interface circuit, each comprising a fast input port...
6035361 Cell bus arbitration device and method arbitrating the same  
A cell bus arbitration device and method arbitrating a cell bus transmitting data in a certain size of packet unit is disclosed. The cell bus arbitration device comprises a filter for outputting...
6029224 Self-contained memory apparatus having diverse types of memory and distributed control  
An apparatus is provided that improves memory storage and access speed by repackaging various types of memories, SRAM, DRAM, and Disk, into a single storage unit. Each unit contains a slice of all...
6026461 Bus arbitration system for multiprocessor architecture  
A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward...
Matches 1 - 50 out of 91 1 2 >