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7529955 Dynamic bus parking  
Systems and methods of power management provide for issuing a power saving message from a processor toward a controller and using the controller to conduct a power saving activity in response to...
7523324 Method and apparatus for improving bus master performance  
A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU...
7522073 Self-adapted bus inversion  
Embodiments of the invention generally provide methods, systems, and articles of manufacture for selecting a data bus inversion (DBI) mode of operation. A comparison circuit of a device may receive...
7460061 Distributed radar data processing system  
A distributed radar data processing system for generating data to be supplied to air traffic control by processing radar data obtained from a radar device, comprises a plurality of data buses...
7451259 Method and apparatus for providing peer-to-peer data transfer within a computing environment  
A method and apparatus for providing peer-to-peer data transfer through an interconnecting fabric. The method and apparatus enable a first device to read and/or write data to/from a local memory of...
7386750 Reduced bus turnaround time in a multiprocessor architecture  
Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus...
7353317 Method and apparatus for implementing heterogeneous interconnects  
Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the...
7350002 Round-robin bus protocol  
A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During...
7349998 Bus control system for integrated circuit device with improved bus access efficiency  
The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal,...
7315913 CPU system, bus bridge, control method therefor, and computer system  
In a system having an arrangement that a CPU ( 101 ) connected to a bus ( 107 ) via bus bridge ( 103 ) and a CPU 102 connected to a bus ( 107 ) via bus bridge ( 104 ), when the bus bridge ( 103 )...
7251702 Network controller and method of controlling transmitting and receiving buffers of the same  
In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from...
7191271 Two level multi-tier system bus  
The present invention is directed to a method and apparatus utilizing a two-level, multi-tier system bus. The multi-tier system bus of the present invention allows for the flow of information to be...
7149828 Bus arbitration apparatus and bus arbitration method  
The present invention is to provide a bus arbitration apparatus and a bus arbitration method not reducing data transfer capability as a whole and preventing a loss of transferred data. It performs...
7133949 Distributed switching method and apparatus  
Switching method and apparatus for assigning a communication grant to a first processing unit in a communication network comprising a plurality of processing units, each processing unit being...
7058742 Method and apparatus for arbitrating common bus by using urgent channel  
A method and apparatus for arbitrating between a plurality of masters for use of a common bus. Arbitration is preferably performed based on an urgency and a predetermined priority of a master...
7039736 Systems and methods for accessing bus-mastered system resources  
Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is...
7039734 System and method of mastering a serial bus  
A method and method of mastering a serial bus. A serial bus is monitored in order to detect a quiescent period on the bus. Responsive to a detection of a quiescent period, bus signals to a first...
7024505 Fair arbitration method in a distributed arbitration system  
A method of communicating between an initial device and a target device connected by a plurality of intermediate segments in a distributed arbitration system is provided. The method includes...
6993612 Arbitration method for a source strobed bus  
A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a...
6990539 Apparatus and method of implementing BREQ routing to allow functionality with 2 way or 4 way processors  
An apparatus for implementing bus request routing to allow functionality with 2 way or 4 way processors, includes a bus configured to provide bus request routing; and a bus request route switching...
6981087 Multi-master and diverse serial bus in a complex electrical system  
A two wire serial bus is connected between different circuit boards in a complex electrical system. The two wire serial bus may be used to receive status information about each of the circuit...
6980314 Method and device for improving utilization of a bus  
An embodiment of a bus management device permits scheduling of transactions to allow concurrent execution of the transactions. Data bus usage is scheduled by setting shift register bits. Each...
6950892 Method and system for managing distributed arbitration for multicycle data transfer requests  
A method and system for managing distributed arbitration for multi-cycle data transfer requests provides improved performance in a processing system. A multi-cycle request indicator is provided to...
6915366 Computer system with a communication bus  
A bus has a local section ( 10 a,b ) and a shared section ( 11 a,b ). An arbiter circuit ( 16 ) issues an arbited grant ( 25 ) to access the shared section ( 11 a,b ) in response to a request ( 22...
6865632 Method and apparatus for arbitration and fairness on a full-duplex bus using dual phases  
A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means.
6839784 Control unit of an I/O node for a computer system including a plurality of scheduler units each including a plurality of buffers each corresponding to a respective virtual channel  
A virtual channel buffer of a transaction scheduler in a computer system I/O node. A control unit includes a plurality of scheduler units. Each scheduler unit may include a first and a second...
6826643 Method of synchronizing arbiters within a hierarchical computer system  
A method of synchronizing arbiters. The method is performed by a computer system that has a first repeater, a second repeater that is coupled to the first repeater, and a third repeater that is...
6742064 Programmable throttle circuit for each control device of a processing system  
A processing system comprises: a shared system resource; a plurality of control devices, each assignable with a task having a predetermined maximum time to complete, the control devices time...
6728618 Method for activating a system for controlling and/or regulating operational sequences in a motor vehicle having several equal-access control units  
A system for controlling and/or regulating operational sequences in a motor vehicle having several equal-access control units for controlling and/or regulating certain functions in the motor...
6721833 Arbitration of control chipsets in bus transaction  
A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second...
6708242 Methods for addressing extended number of peripheral devices over peripheral bus  
The present invention provides methods for addressing an extended number of peripheral devices over a bus. A bus having an N-bit datapath is provided in a computer system. An extended address space...
6704820 Unified cache port consolidation  
A method and apparatus consolidate ports on a unified cache. The apparatus uses plurality of access connections with a single port of a memory. The apparatus comprises multiplexor and a logic...
6684279 Method, apparatus, and computer program product for controlling data transfer  
A method, apparatus, and computer program product are described for controlling data transfer. A next data packet to be transferred is retrieved. A determination is made regarding whether a data...
6675246 Sharing arbiter  
The Sharing arbiter is an arbiter which, under certain conditions, permits two or more Done signals to be received before the Sharing arbiter issues a grant signal and, under certain conditions, is...
6675245 Apparatus and method for providing round-robin arbitration  
The present invention provides round-robin arbitration between requests for access to a shared resource such as a data bus ( 7 ), shared by a plurality of hardware modules. A central counter ( 1 )...
6636915 Cell bus distributed arbitration system and method  
A cell bus arbitration system comprises a data bus and a plurality of modules operative for sending data in data cell. The modules are connected to the data bus and each one of the modules is in...
6523076 Method and apparatus for synchronizing multiple bus arbiters on separate chips to give simultaneous grants for the purpose of breaking livelocks  
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch,...
6490644 Limiting write data fracturing in PCI bus systems  
A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous...
6487617 Source-destination re-timed cooperative communication bus  
A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when the addressed storage location in the data...
6480917 Device arbitration including peer-to-peer access arbitration  
A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI...
6453376 Method for implementing scheduling mechanisms with selectable resource modes  
A method for implementing scheduling mechanisms with selectable resource modes comprises at least one resource characterization set that includes a plurality of resource characterizations that each...
6442632 System resource arbitration mechanism for a host bridge  
A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority...
6434636 Method and apparatus for performing high bandwidth low latency programmed I/O writes by passing tokens  
A method and apparatus performs high bandwidth low latency programmed I/O (PIO) write operations by passing tokens. A computer system in accordance with the present invention includes a plurality...
6421752 Electronic apparatus  
An electronic apparatus uses a bus conductor driven by wired logic to arbitrate between stations. When arbitration is decided, the apparatus switches to a higher speed mode by supplying additional...
6415369 Shared devices and memory using split bus and time slot interface bus arbitration  
A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the...
6411218 Priority-encoding device selection using variable arbitrary rankings  
In the context of a bus-mastering system, a device selector selects the device to control the bus by assigning “combined” priority values to the devices and selecting the device with the...
6393508 Method and apparatus for multiple tier intelligent bus arbitration on a PCI to PCI bridge  
The method of the present invention includes maintaining a first tier 101 and a second tier 102 of devices 30 that have access to a secondary bus 42 that a PCI to PCI bridge 38 services....
6385680 Method for flexibly allocating request/grant pins between multiple bus controllers  
One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by...
6374319 Flag-controlled arbitration of requesting agents  
A method and an system are provided for servicing a plurality of agents requesting access to a bus. The agents are arranged in a hierarchical order of groups, each having first and second pairs of...
6363447 Apparatus for selectively encoding bus grant lines to reduce I/O pin requirements  
One embodiment of the present invention provides an apparatus that selectively encodes bus grant lines to reduce I/O pin requirements. This apparatus includes a semiconductor chip with bus...
Matches 1 - 50 out of 177 1 2 3 4 >