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7620760 Non-high impedence device and method for reducing energy consumption  
A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit...
7613740 Control of a data replication engine using attributes associated with a transaction  
A data replication engine is controlled in a system that replicates data associated with a plurality of transactions from a source database to a target database. The system includes a change queue...
7606958 Interrupt control method, interrupt control apparatus and interrupt control medium  
Once accepting an interrupt, the control is such as to not accept any interrupt including that highest priority within the group to which the interrupt about to be processed belongs by referring to...
7603496 Buffering data during data transfer through a plurality of channels  
A buffer is disclosed for storing data being transferred using a plurality of control channels, a data item of said data being transferred between a data source and a data destination using one of...
7587542 Device adapted to send information in accordance with a communication protocol  
A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a...
7580361 Network system, information processor and electronic apparatus  
In the present network system, a printer 10 periodically transmits an update request at different timings respectively to an apparatus management PC 30 and to a directory service 50 which are...
7536496 Method and apparatus for transmitting data in an integrated circuit  
A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a...
7533206 Resource management device  
A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given...
7532636 High bus bandwidth transfer using split data bus  
Methods and apparatus for achieving high bus bandwidth transfer using a split data bus. A data bus is split into multiple segments whose access is, individually controlled by an arbitration control...
7529955 Dynamic bus parking  
Systems and methods of power management provide for issuing a power saving message from a processor toward a controller and using the controller to conduct a power saving activity in response to...
7526595 Data path master/slave data processing device apparatus and method  
An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data...
7525986 Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools  
Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input...
7523324 Method and apparatus for improving bus master performance  
A method and apparatus are disclosed for performing dynamic arbitration of memory accesses by a CPU and at least one bus master interface module based on, at least in part, monitoring a CPU...
7512729 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency  
A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes...
7512723 Queued interface devices, multi-core peripheral systems, and methods for sharing a peripheral in a multi-core system  
A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second...
7508723 Buffered memory device  
A memory module having a DRAM device configured to generate a low DQS state on a DQS line, and a buffer coupled to the DRAM device, the buffer having a plurality of drivers, wherein the buffer is...
7500035 Livelock resolution method  
A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit...
7500034 Multiple integrated circuit control  
In an implementation of multiple integrated circuit control, a multiple integrated circuit controller initiates and controls data transactions between the multiple integrated circuit controller and...
7490185 Data processing system, access control method, and access control device  
A data processing system able to raise the access efficiency to a memory when a plurality of processor access to the memory will be provided. An arbitration program executed by one input/output...
7487276 Bus arbitration system  
A circuit arrangement for bus arbitration alters the sequence in which device requests are arbitrated with respect to each other and to a previous arbitration sequence. To this end, an arbiter...
7478183 Method and system for n dimension arbitration algorithm—scalable to any number of end points  
A method, a system and a computer programmable product have been provided for arbitrating bus cycles among a plurality of device nodes. Requests for bus grant are received from the device nodes....
7475302 Decoded match circuit for performance counter  
A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match...
7467245 PCI arbiter  
A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data...
7464207 Device operating according to a communication protocol  
A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a...
7447817 Method and system for processing arbitration requests  
Method and system for arbitrating between plural arbitration requests is provided. The system includes a plurality of first stage arbiters that receive plural arbitration requests and a signal that...
7444668 Method and apparatus for determining access permission  
A method and apparatus for determining access protection ( 96 ) includes receiving a plurality of access requests ( 84 ) corresponding to a plurality of masters ( 12, 14 ), determining access...
7444447 Arrangement, device and method for controlling bus request signal generation  
A device, arrangement and method may control bus request timing to disperse bus access timing, so that adverse effects of concentration-on-bus phenomenon may be avoided. The device may include a...
7441059 Method and device for data communication  
A device for data communication between a first host device or a further host device and at least one client device along a shared transmission path includes a first host device, which includes a...
7437494 Systems and methods for assigning an address to a network device added to an existing network  
The present invention provides systems, methods, and bus controllers for establishing communication with various network systems located on a network system. Importantly, the systems, methods, and...
7428607 Apparatus and method for arbitrating heterogeneous agents in on-chip busses  
A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and...
7426709 Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system  
An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to...
7412556 Method and system for master devices accessing slave devices  
Techniques for multiple master devices accessing one or more slave devices via a single data bus are disclosed. According to one aspect of the techniques, a bus controller coupled between the...
7412550 Bus system with protocol conversion for arbitrating bus occupation and method thereof  
A bus system including a bus arbiter and a plurality of masters. The bus arbiter grants bus control to one of the plurality of masters. When a master with bus control sends a read command, bus...
7395360 Programmable chip bus arbitration logic  
Methods and apparatus are provided for implementing a bus arbitration priority encoding scheme with fairness. Bus arbitration logic is connected to multiple primary components or devices. The...
7386750 Reduced bus turnaround time in a multiprocessor architecture  
Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus...
7370161 Bank arbiter system which grants access based on the count of access requests  
Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the...
7328292 Arbitration method and device  
In an arbitration device, the entire transfer efficiency is improved without increasing the operating frequency and the number of pins. An overflow monitor mechanism generates an alarm once...
7328286 Automatic addressing on bus systems  
In a method and apparatus for automatic address allocation among control devices connected to a bus system in a vehicle, and address allocation period sending a message on the common data bus line....
7315909 Hierarchized arbitration method  
An arbitration method, for a data bus in an architecture having n functional blocks, regulates access to the bus. The method includes: receiving, at one of plural agents, information from one of...
7305499 DMA controller for controlling and measuring the bus occupation time value for a plurality of DMA transfers  
The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of...
7302699 Logged-in device and log-in device  
A management agent ME 1 of a target T 1 receives a request of log-in from an initiator of interest and determines whether or not a number of initiators that currently log in the target T 1 ...
7299311 Apparatus and method for arbitrating for a resource group with programmable weights  
A system and method for arbitrating for access to a resource group between agents according to a respective programmable weight for each agent. For each agent, a programmable mapping module...
7290075 Performing arbitration in a data processing apparatus  
An apparatus for arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The...
7281071 Method for designing an initiator in an integrated circuit  
A method for designing an integrated circuit where the integrated circuit includes a plurality of modules and where each module includes an initiator port and a target port coupled to a distributed...
7275119 Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus  
A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an...
7246052 Bus master and bus slave simulation using function manager and thread manager  
The system simulator comprises master simulators 1 f , 1 s , 2 f and 2 s for simulating a bus master, a slave simulator L for simulating a bus slave, a function manager F for sequentially...
7237071 Embedded symmetric multiprocessor system with arbitration control of access to shared resources  
A single chip, embedded symmetric multiprocessor (ESMP) having parallel multiprocessing architecture composed of identical processors includes a single program memory. Program access arbitration...
7237050 Multi-channel serial advanced technology attachment control system and control card thereof  
A multi-channel serial advanced technology attachment (SATA) control system and control card thereof includes a first SATA control module, a first access-grant arbitration unit, a second SATA...
7231479 Round robin selection logic improves area efficiency and circuit speed  
A method and apparatus are provided for efficiently operating a round robin arbitration system in a given computer system. The system utilizes a series of banks of requestors and pointer. The banks...
7231477 Bus controller  
A bus controller is provided including a processing means for performing processings of levels having cycle numbers which are different dependent on requesters which respectively issue an access...
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