Matches 301 - 350 out of 545 < 1 2 3 4 5 6 7 8 9 10 11 >
Match Document Document Title
5983301 Method and system for assigning a direct memory access priority in a packetized data communications interface device  
In a PCI-interface device (20), assigning highest DMA channel (74) priority is based on the DMA channel number associated with the data transfer currently active on the physical media interface....
5983304 Buffer flush controller of a peripheral component interconnect-peripheral component interconnect bridge  
A buffer flush controller, of a peripheral component interconnect-peripheral component interconnect bridge (PPB), includes a first compounding circuit, a first state machine, a second state...
5978875 Apparatus and method for scheduling use of bus  
A continuous data server includes a storage unit connected to a buffer memory which is in turn connected to a plurality of communication control units which transfer data of the buffer memory to a...
5978867 System for counting clock cycles stolen from a data processor and providing the count value to a second processor accessing the data processor cycle resources  
An apparatus and method are implemented to track and manage system cycles stolen from a data processor by other processors in a multiprocessor data processor system. The apparatus and method...
5974488 Method and apparatus for transmission of signals over a shared line  
A semiconductor component is described which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component...
5974497 Computer with cache-line buffers for storing prefetched data for a misaligned memory access  
In a computer including two buses, a main memory, a write back cache, and a peripheral device, a method and apparatus for providing an inter-bus buffer to support successive main memory accesses...
5968150 Processor element having a plurality of CPUs for use in a multiple processor system  
A processor for constructing a single processor system or multiprocessor system comprises, within a base processor element constituting the processor, two CPU with associated local memories, a...
5968153 Mechanism for high bandwidth DMA transfers in a PCI environment  
A method and apparatus for maximizing the performance of DMA transfers over a PCI™ bus are provided which includes a Per-Channel Retry count, Double Buffer Management, Wait Enable functionality,...
5968154 Distributed priority arbitrating method and system in multi-point serial networks with different transmission rates  
This invention presents the serial arbitration method and system for rapidly and accurately identifying a station with the highest priority when a plurality of stations with different transmission...
5966306 Method for verifying protocol conformance of an electrical interface  
A method and technique for verifying bus protocol in the design of integrated circuits. A correctness evaluator receives simulation results from a monitor file and prediction information generated...
5960179 Method and apparatus extending coherence domain beyond a computer system bus  
In a networked computer system that includes an omnibus system coupled to a plurality of workstation/computer subsystems, an optimal global reordering of transactions seeking Address Bus access is...
5954809 Circuit for handling distributed arbitration in a computer system having multiple arbiters  
An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable...
5956493 Bus arbiter including programmable request latency counters for varying arbitration priority  
A computer system is provided for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit...
5950229 System for accelerating memory bandwidth  
A computer system and method process memory requests for access to a computer memory. The computer system arbitrates between current memory requests based on an immediately previous memory request...
5948094 Method and apparatus for executing multiple transactions within a single arbitration cycle  
A method of arbitrating among bus agents, wherein a bus agent is permitted multiple transactions within a single arbitration cycle. An arbitration event is initiated, and a request from a bus agent...
5944809 Method and apparatus for distributing interrupts in a symmetric multiprocessor system  
A distributed interrupt controller system for use in a multiprocessor environment, having at least two local programmable interrupt controllers (LOPICs) coupled to at least one central programmable...
5943483 Method and apparatus for controlling access to a bus in a data processing system  
A method and apparatus for controlling access to a bus. A target having a period of unavailability is identified. A master device requesting access to the bus to initiate a data transfer between...
5935234 Method and system for controlling access to a shared resource in a data processing system utilizing pseudo-random priorities  
A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by...
5935230 Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs  
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID...
5931932 Dynamic retry mechanism to prevent corrupted data based on posted transactions on the PCI bus  
A method and apparatus to prevent data from being corrupted prior to reaching the final destination is provided. The method and apparatus monitors the status of posted write transactions and...
5933609 Method and system for hot docking a portable computer to a docking station via the primary PCI bus  
A portable computer and corresponding docking station, where the portable computer may be inserted into or removed from the docking station without concern relating to the state of either the...
5931931 Method for bus arbitration in a multiprocessor system  
One aspect of the invention relates to a method for arbitrating simultaneous bus requests in a multiprocessor system having a plurality of devices which are coupled to a shared bus. In one version...
5933616 Multiple bus system bus arbitration according to type of transaction requested and the availability status of the data buffer between the buses  
A computer system is provided wherein a bus master generates a signal indicative of the type of cycle it plans to initiate when requesting bus ownership. Other bus masters may be configured to...
5930487 PCI bus master with cascaded PCI arbitration  
A PCI bus master supporting cascading PCI arbitration. The cascading arbitration allows another PCI initiator on the same bus to share the request and grant signal pair to/from the PCI central...
5930485 Deadlock avoidance in a computer system having unordered slaves  
A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment,...
5926628 Selectable priority bus arbitration scheme  
A method and system for arbitrating access to a component of a computer have been disclosed the method and system include an arbitration unit for granting access to the component; and a plurality...
5923859 Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus  
Arbitration circuitry in a computer system having a plurality of arbiters for arbitrating requests from bus masters on a PCI bus and an EISA bus. Each of the PCI and EISA buses have a plurality of...
5920892 Method and system for inhibiting transfer of duplicate write addresses in multi-domain processor systems with cross-bus architecture to reduce cross-invalidation requests  
A two domain digital network with each domain having its own system bus and its own bus exchange module permits Write operation addresses to be passed between domains. Each bus exchange module...
5918055 Apparatus and method for managing digital resources by passing digital resource tokens between queues  
A method of managing digital resources of a digital system includes the step of reserving token values for certain digital resources in the digital system. A selected token value in a...
5915102 Common arbiter interface device with arbitration configuration for centralized common bus arbitration  
A method and apparatus for configuring a centralized arbitration scheme for a commonly accessed communication bus using arbiter devices with arbitration control circuitry included therein. The...
5911052 Split transaction snooping bus protocol  
A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory,...
5907688 Smart arbitration for non-symmetric data streams  
A method and apparatus for selecting a data stream in an access to a shared bus in a computer system. The method begins by requesting access to the shared bus. An evaluation of whether a first or a...
5907689 Master-target based arbitration priority  
A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the...
5905889 Resource management system using next available integer from an integer pool and returning the integer thereto as the next available integer upon completion of use  
A system and method for managing access by a user to a reusable resource. An integer pool is provided, along with program and hardware structures for obtaining an integer from the integer pool, for...
5901295 Address and data bus arbiter for pipelined transactions on a split bus  
An arbiter employs both an address bus arbiter and a data bus arbiter for supporting pipelined, split bus transactions. The address arbiter may be implemented using a state machine. A first through...
5901296 Distributed scheduling for the transfer of real time, loss sensitive and non-real time data over a bus  
Data is transferred over a bus from one device to another, or between one device and another system resource, such as a central processor. This data is classified into one of several types. "Hard...
5901297 Initialization mechanism for symmetric arbitration agents  
An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each...
5898857 Method and system for interfacing an upgrade processor to a data processing system  
A data processing system is disclosed which includes a first processor having an m-byte data width, an n-byte data bus, where n is less than m, and a second processor electrically coupled to the...
5898694 Method of round robin bus arbitration  
An arbitration unit contains a method of arbitration which includes distributed arbitration, a priority mechanism to support different classes of traffic, a unique arbitration ID bits for each...
5898847 Bus arbitration method and appparatus for use in a multiprocessor system  
A bus arbitration method for use in a multiprocessor system having a plurality of agents and a system bus, for determining a sampling point at which bus arbitration-related signals on the system...
5894562 Method and apparatus for controlling bus arbitration in a data processing system  
A method of controlling bus arbitration using an arbitration bit to lock ownership of the bus and prevent bus grants pending completion of a predetermined sequence. In a data processing system (15)...
5889969 Logical bus structure including plural physical busses for a multiprocessor system with a multi-level cache memory structure  
An improved multiple bus system for a multiprocessor computer system is disclosed for a computer system having a multiple level cache memory structure. The system includes one or more logical...
5881256 Bus interface unit capable of simultaneously proceeding with two bus cycles in a high-performance microprocessor  
A bus interface unit of a microprocessor which can simultaneously process bus cycle's requests coming from various pipelines during for one cycle in the pipelined high-performance microprocessor of...
5875309 Arbitration system using linked table  
A computer network system containing a concentrator with a backplane that has a plurality of lines. The backplane contains data lines and control lines for managing and organizing the transfer of...
5872941 Providing data from a bridge to a requesting device while the bridge is receiving the data  
A computer system includes a data storage device on a first data bus, a requesting device that initiates a delayed request on a second data bus, and a bridge device that delivers the delayed...
5870570 Multiple bus agent integrated circuit device for connecting to an external bus  
A multiple peripheral component interconnect (PCI) agent integrated circuit device for connecting to an external PCI bus. In one embodiment, the present multiple PCI agent integrated circuit device...
5867670 Self-control type bus arbitration circuit and arbitration method therefor  
A self-control type bus arbitration circuit and an arbitration method are disclosed, in which a bus arbiter is not needed, but entities commonly connected to a bus share 3 kinds of information, so...
5862356 Pipelined distributed bus arbitration system  
The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a...
5862353 Systems and methods for dynamically controlling a bus  
Bus performance in a computer system having multiple devices accessing a common shared bus may be improved by increasing throughput and decreasing latency while accounting for dynamic changes in...
5859985 Arbitration controller for providing arbitration on a multipoint high speed serial bus using drivers having output enable pins  
An arbitration controller provides arbitration on a multipoint, high speed serial bus with a plurality of drivers. Each driver includes a data input pin, an output enable pin, and an output pin....
Matches 301 - 350 out of 545 < 1 2 3 4 5 6 7 8 9 10 11 >