Matches 101 - 150 out of 545 < 1 2 3 4 5 6 7 8 9 10 11 >
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7000049 Systems and methods for reliably selecting bus mastership in a fault tolerant manner  
A system for selecting bus mastership in a multi-master system includes master devices and at least one slave device. The master devices generate control signals relating to bus mastership in the...
7000059 Integrated PCI interface card and bus system thereof  
The present invention discloses an integrated PCI interface card and the bus system thereof. The integrated PCI interface card of the present invention includes at least two bus masters, a control...
7000131 Apparatus and method for assuming mastership of a bus  
The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one...
6996656 System and method for providing an arbitrated memory bus in a hybrid computing system  
A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the...
6990537 System and method for controlling multi-component communications via a bus by causing components to enter and exit a high-impedance state  
A method for controlling communication on a bus connecting a first processor, a second processor, and a device. The method transmits a first control signal from the first processor to the second...
6990541 Arbitration unit for prioritizing requests based on multiple request groups  
An arbitration unit includes an input unit, a selection unit and an output unit. The input unit may receive a plurality of input requests on a plurality of inputs. The selection unit may prioritize...
6981082 On chip streaming multiple bus protocol with dedicated arbiter  
The present invention creates dedicated point-to-point or point-to-multipoint links between different devices along plural busses. Synchronized clocks to each device enable proper timing of read...
6981081 Method for SMI arbitration timeliness in a cooperative SMI/driver use mechanism  
A Bus Driver implements an arbitration mechanism to allow both the system management interrupt (SMI) and the Bus Driver to cooperatively use a Bus host controller hardware. This mechanism employs a...
6978329 Programmable array-based bus arbiter  
A bus arbiter for arbitrating bus access requests from N bus requestor devices. The bus arbiter comprises N one-hot registers, each one-hot register associated with a corresponding bus requester...
6976106 Method and apparatus for speculative response arbitration to improve system latency  
A method and apparatus for speculative response arbitration to improve system latency have been described.
6976108 System on a chip having a system bus, an external bus, and a bus arbiter with programmable priorities for both buses, software, and method for assigning programmable priorities  
A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter...
6970912 Computer system having a plurality of computers each providing a shared storage access processing mechanism for controlling local/remote access to shared storage devices  
A computer system having a plurality of computers connected to each other by a computer coupling mechanism. Each computer includes a processor, memory, I/O device, disk control mechanism, computer...
6968407 System and method for managing CPCI buses in a multi-processing system  
The present invention relates to a system and method for managing Compact Component Interconnect (CPCI) buses in a multi-processing system. More particularly, the present invention improves...
6961793 Bus arbiter and bus access arbitrating method  
A bus arbiter for a group of masters and a bus access control method. An arbitration priority control section output basic priority data for each of the masters. An arbitration priority generating...
6959354 Effective bus utilization using multiple bus interface circuits and arbitration logic circuit  
In one embodiment of the present invention, a bus controller is used in a multi-bus system having first and second buses. The bus controller includes first and second bus interface circuits, a...
6954811 Arbiter for an input buffered communication switch  
An arbiter for a switch maintains a pair of counters for each flow of traffic at each input port: one counter (also called “first counter”) to indicate an ideal transfer of traffic, and another...
6952748 Voltage request arbiter  
Various embodiments of a circuit and method for arbitrating voltage requests in a computer system are disclosed. In a first embodiment, one or more devices in a computer system assert a plurality...
6952747 Method of delaying bus request signals to arbitrate for bus use and system therefor  
In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the...
6948019 Apparatus for arbitrating non-queued split master devices on a data bus  
A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An...
6944696 Data processing processor  
A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use...
6944698 Method and apparatus for providing bus arbitrations in a data processing system  
A method and apparatus for providing bus arbitrations in a multiprocessor system is disclosed. A computer system includes a common bus that is shared by multiple cores, such as processors. A...
6922749 Apparatus and methodology for an input port of a switch that supports cut-through operation within the switch  
An input port is described having an input policing unit that checks if a virtual lane has a sufficient number of credits to carry an input packet received by the input policing unit. The input...
6917996 Bus control system and method of controlling bus  
An external bus control device 2 has first and second bus controllers 15, 16 and an external bus arbiter 17 . The bus controllers 15, 16 correspond to devices (for example, SRAM, DRAM)...
6917991 Method of and system for efficiently tracking memory access by direct memory access controller  
The debug controller makes an efficient use of memory in tracing the direct memory access by the processor and the direct memory access controller for the purpose of debugging. The direct memory...
6915366 Computer system with a communication bus  
A bus has a local section ( 10 a,b ) and a shared section ( 11 a,b ). An arbiter circuit ( 16 ) issues an arbited grant ( 25 ) to access the shared section ( 11 a,b ) in response to a request ( 22...
6901487 Device for processing data by means of a plurality of processors  
A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per...
6898766 Simplifying integrated circuits with a common communications bus  
When integrating a peripheral, it is common practice to use a fully custom design. Custom designs typically optimize performance, size, and energy usage. However, custom designs are more expensive...
6895458 Opcode to turn around a bi-directional bus  
A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data...
6892259 Method and apparatus for allocating computer bus device resources to a priority requester and retrying requests from non-priority requesters  
A target device in a computer bus system allocates resources by selecting a priority requester for allocation of scarce resources. In a non-bus arbiter configuration, the first initiator device to...
6883051 Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses  
In one embodiment of the present invention, a slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave devices...
6883050 Optimized POD module/host interface  
An interface between a point of deployment (POD) module and a host device, such as a set-top terminal for cable television selectively integrates the POD module and the host such that th POD module...
6877053 High performance communication architecture for circuit designs using probabilistic allocation of resources  
A circuit comprising a plurality of components sharing at least one shared resource, and a lottery manager. The lottery manager is adapted to receive request for ownership for the at least one...
6877057 Information handling system with dynamic interrupt allocation apparatus and methodology  
An information handling system is provided which includes a dynamic interrupt router for balancing interrupt assignments among a plurality of devices requesting interrupt assignments. The system...
6865632 Method and apparatus for arbitration and fairness on a full-duplex bus using dual phases  
A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means.
6865630 Apparatus and method of preventing congestion in message transmission system  
An apparatus and a method of arbitrating access to a common bus, for a first set of modules included in a message transmission system, are disclosed. Using the apparatus and method of the present...
6851005 Apparatus and method for implementing raid devices in a cluster computer system  
Apparatus and methods are provided for efficiently implementing logical-device reservations in a cluster computer system. The apparatus includes cooperating controllers programmed in firmware...
6842669 Component interface module  
A component interface module (CIM) arbitrates through priority logic component command signals from redundant systems and integrates the selected priority command signal with component feedback...
6839784 Control unit of an I/O node for a computer system including a plurality of scheduler units each including a plurality of buffers each corresponding to a respective virtual channel  
A virtual channel buffer of a transaction scheduler in a computer system I/O node. A control unit includes a plurality of scheduler units. Each scheduler unit may include a first and a second...
6832280 Data processing system having an adaptive priority controller  
The present invention relates generally to data processors and more specifically, to data processors having an adaptive priority controller. One embodiment relates to a method for prioritizing...
6823424 Rebuild bus utilization  
A technique for selecting events associated with a hot-plug operation. More specifically, a programmable configuration register may be used to provide a mechanism for periodically scheduling...
6823408 Electronic equipment, and method for controlling state of physical layer circuit therefor  
A system is designed to avoid problems that may occur if a physical layer misunderstands the kind of signal it receives and erroneously changes its state to a suspend state. When a node B receives...
6816922 Digital signal processor with a byte DMA controller  
A digital signal processor includes a byte direct memory access (DMA) controller and an external memory controller, both of which are coupled to each other. The external memory controller is...
6816934 Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol  
A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a...
6813767 Prioritizing transaction requests with a delayed transaction reservation buffer  
In one embodiment of the invention, a transaction queue stores a transaction request and issues a stream transaction for the stored transaction request when a slot in a set of active stream...
6810455 Bus arbitration system and method for carrying out a centralized arbitration with independent bus request and grant lines  
Disclosed is a bus arbitration system and method which assume that each operation using the bus requires from one to five bus clock cycles. Each potential bus master has a dedicated bus request...
6807593 Enhanced bus architecture for posted read operation between masters and slaves  
An electronic bus architecture for supporting posting of read requests by multiple master devices to multiple slave devices. Sideband signals added to the underlying master bus architecture permit...
6804736 Bus access arbitration based on workload  
A computer system with a bus arbitration system adaptively assigns priority to devices on the bus based upon workload. A bus arbiter receives request signals from bus devices that require bus...
6801978 Crossbar system with increased throughput  
A requester includes an output data register which retains a data piece to be output to a relay register of a crossbar, and two request registers which output a request corresponding to the data...
6775717 Method and apparatus for reducing latency due to set up time between DMA transfers  
A method and apparatus for reducing latency due to set up time between DMA transfers are described. The method comprises initiating arbitration of DMA channel requests prior to completion of a...
6775727 System and method for controlling bus arbitration during cache memory burst cycles  
A bus arbiter ( 34 ) monitors characteristics associated with the type of information that is transferred via a global data bus ( 12 ) during burst transactions of information. A user-controlled...
Matches 101 - 150 out of 545 < 1 2 3 4 5 6 7 8 9 10 11 >