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7231477 |
Bus controller
A bus controller is provided including a processing means for performing processings of levels having cycle numbers which are different dependent on requesters which respectively issue an access...
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7231479 |
Round robin selection logic improves area efficiency and circuit speed
A method and apparatus are provided for efficiently operating a round robin arbitration system in a given computer system. The system utilizes a series of banks of requestors and pointer. The banks...
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7219179 |
***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Apparatus for arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatus
An apparatus for arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The...
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7209998 |
Scalable bus structure
A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be...
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7203779 |
Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus
A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to...
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7203781 |
Bus architecture with primary bus and secondary or slave bus wherein transfer via DMA is in single transfer phase engagement of primary bus
A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus....
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7181558 |
Avoidance of extended bus occupancy through simple control operation
A shared bus system includes a bus, a first circuit which accesses the bus, a second circuit which shares the bus with the first circuit, and accesses the bus, a counter circuit which is provided...
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7174401 |
Look ahead split release for a data bus
A data bus transfers data between at least one slave device and a plurality of master devices, and an arbiter grants access to each of the master devices. The slave device includes look-ahead...
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7174403 |
Plural bus arbitrations per cycle via higher-frequency arbiter
An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or...
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7167939 |
Asynchronous system bus adapter for a computer system having a hierarchical bus structure
A computer system having a hierarchical bus structure that allows decoupling of a local bus from a global bus thereof. Decoupling of the local bus is achieved through use of an asynchronous system...
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7165131 |
Separating transactions into different virtual channels
In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third...
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7143220 |
Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies
A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and...
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7143221 |
Method of arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatus
A method of arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality...
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7127539 |
Statistic method for arbitration
A statistic method for arbitration is provided, implementing in an arbitration system comprising a bus, a main controller connected to the bus, and a plurality of peripheral devices able to be...
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7127545 |
System and method for dynamically loadable storage device I/O policy modules
Systems, methods, apparatus and software can implement a multipathing driver using dynamically loadable device policy modules that provide device specific functionality for providing at least one...
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7124229 |
Method and apparatus for improved performance for priority agent requests when symmetric agent bus parking is enabled
A method and apparatus for improved performance for handling priority agent bus requests when symmetric agent bus parking is enabled is disclosed. In one embodiment, a modified priority agent may...
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7124410 |
Distributed allocation of system hardware resources for multiprocessor systems
A method is provided for allocating system resources across multiple nodes of a system communicating through a hardware device. The method provides for allocation of transaction units or...
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7120714 |
High-speed starvation-free arbiter system, rotating-priority arbiter, and two stage arbitration method
A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requestors in accordance with a first arbitration scheme and a second-stage arbiter to grant...
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7107376 |
Systems and methods for bandwidth shaping
Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource...
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7107375 |
Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology
An arbitration elimination scheme for a bus. In a preferred embodiment, a programmable counter determines when a SCSI bus idle condition is reached and when a portion of an arbitration window for...
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7107374 |
Method for bus mastering for devices resident in configurable system logic
A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a...
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7107365 |
Early detection and grant, an arbitration scheme for single transfers on AMBA advanced high-performance bus
A system on a chip (SOC) bus architecture may comprise a plurality of masters operable to request communications over a AMBA-type bus. An arbiter may receive requests and burst control signals...
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7103690 |
Communication between logical macros
A connection is provided between logical macros to allow prioritization of operations in accordance with an arbitration scheme that distinguishes between operations based on such factors as...
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7096293 |
Dynamic bus arbitration method and bus arbiter
A method of arbitrating a system bus shared by a CPU, which is a first master device, and second and third master devices comprises storing a first bus occupancy rate for each master device and a...
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7093153 |
Method and apparatus for lowering bus clock frequency in a complex integrated data processing system
A data processing system ( 100 ) comprises a system bus ( 120 ), a plurality of devices ( 110, 150, 160, 170 ) coupled to the system bus ( 120 ), a bus monitor circuit ( 140 ), and a clock...
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7085865 |
I/O throughput by pre-termination arbitration
The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention...
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7085864 |
Method and structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter
An overrun data handling circuit in a SCSI initiator and an overrun data handling method automatically handle Packetized SCSI Protocol data overruns. A multi-data channel host adapter includes the...
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7080175 |
Network system
A network system is formed with a parent station and programmable controllers and a programmable display devices serving as child stations connected to a single general-purpose serial communication...
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7080174 |
System and method for managing input/output requests using a fairness throttle
A system and method for providing a desired degree of fairness of access to data transfer resources by a plurality of command-initiating bus agents. A bus arbiter allocates general ownership of the...
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7076586 |
Default bus grant to a bus agent
A system may include two or more agents, one of which may be identified as a default agent. If none of the agents arbitrate for the bus, the default agent may be given a default grant of the bus....
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7073003 |
Programmable fixed priority and round robin arbiter for providing high-speed arbitration and bus control method therein
In a programmable fixed priority and round-robin arbiter and a bus control method of the same, the arbiter includes, an HPRIF rotating unit, a request-reordering unit, a request-selecting unit, and...
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7065594 |
Method and apparatus of allocating minimum and maximum bandwidths on a bus-based communication system
Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the...
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7062588 |
Data processing device accessing a memory in response to a request made by an external bus master
A data processing device exchanges data between a memory and an external bus master. The memory is connected to the data processing device via a first bus so as to store data. The external bus...
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7054970 |
Bus arbiter for integrated circuit systems
Systems and methods for bus arbitration in an integrated circuit system, which prevent discrepancies of bus occupation rates (or the number of bus occupancies) and which provide programmable bus...
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7054969 |
Apparatus for use in a computer system
Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module...
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7051133 |
Arbitration circuit and data processing system
An arbitration circuit and a data processing system which ensure fair bus access are provided. An arbitration circuit ( 1 ) has a priority check block ( 21 ) and a round robin block ( 22 ). The...
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7051135 |
Hierarchical bus arbitration
Methods, apparatus, and systems are presented for arbitrating access to a shared resource involve deciding whether to grant access to the shared resource to at least one of a first plurality of...
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7051132 |
Bus system and path decision method therefor
A bus system and a method of deciding a data transmission path are provided. The bus system includes a plurality of functional blocks; a ring bus which transmits data in a single direction; an...
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7051134 |
Daisy chained ATA host controllers in a single PCI device
Implementing daisy chained ATA host controllers in a single PCI device. The present invention discloses a PCI card that includes a plurality of dominant chips, each of the dominant chips supporting...
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7039748 |
Memory mapped I/O bus selection
A mechanism and method for redefining an application specific integrated circuit's I/O bus structure in real-time. The mechanism includes an address map block, a state machine block, and a bus...
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7039736 |
Systems and methods for accessing bus-mastered system resources
Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is...
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7032046 |
Resource management device for managing access from bus masters to shared resources
A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for...
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7028118 |
Multi-channel buffered serial port debugging
In digital signal processors serial data is passed in out and of the chip in a time division multiplexed (TDM) fashion. The TDM stream consists of many independent channels of serial data. The...
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7028117 |
Structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter
An overrun data handling circuit in a SCSI initiator automatically handles Packetized SCSI Protocol data overruns. A multi-data channel host adapter includes the overrun data handling circuit that...
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7016996 |
Method and apparatus to detect a timeout condition for a data item within a process
A method for detecting a timeout condition for a data item (e.g., a request) within the process (e.g., within an arbitration process) includes maintaining a current time as a first N-bit binary...
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7007121 |
Method and apparatus for synchronized buses
A bus arbiter controls the bus frequency in a system that includes a plurality of bus masters and a plurality of slaves. The bus frequency is determined according to the internal frequency of the...
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7007124 |
Image processing system, and semiconductor device and digital still camera apparatus using image processing system
A data processing system includes: at least one function module connected to a single system bus; a data transfer controller which outputs a first bus use permission request signal based on a data...
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7007122 |
Method for pre-emptive arbitration
An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for...
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7007123 |
Binary tree arbitration system and method using embedded logic structure for controlling flag direction in multi-level arbiter node
A binary-tree-based arbitration system and methodology with attributes that approximate a Generalized Processor Sharing (GPS) scheme for rendering fairer service grants in an environment having a...
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7002928 |
IEEE 1394-based protocol repeater
Systems and methods consistent with the present invention connect a remote device to a IEEE 1394-based network through an intervening telephone line, thereby enabling the remote device to...
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