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7610421 Bus request control circuit  
A bus request control circuit provided in a signal processing circuit having a higher priority in an arbitration circuit includes a request signal transmitting section which transmits a request...
7590784 Detecting and resolving locks in a memory unit  
In one embodiment, the present invention includes an apparatus having a first counter to count dispatches of a senior request in a memory unit, a second counter to count cycles of a processor...
7558895 Interconnect logic for a data processing apparatus  
An interconnect logic and method are provided for controlling transaction reordering by slave logic units coupled to the interconnect logic. The interconnect logic couples master logic units and...
7546399 Store and forward device utilizing cache to store status information for active queues  
In general, in one aspect, the disclosure describes an apparatus capable of queuing and de-queuing data stored in a plurality of queues. The apparatus includes a status storage device to track...
7529869 Mixed-signal single-chip integrated system electronics for data storage devices  
An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated...
7526590 Systems and methods for remote pipe resource management in wireless adapters  
Embodiments include systems and methods for management of RPIPES in a Wireless Universal Serial Bus (WUSB) environment comprising at least one WUSB device. RPIPE management computer code is...
7523268 Reducing number of rejected snoop requests by extending time to respond to snoop request  
A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if...
7519755 Combined command and response on-chip data interface for a computer system chipset  
An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when...
7519752 Apparatus for using information and a count in reissuing commands requiring access to a bus and methods of using the same  
In a first aspect, a first method of reissuing a command involving bus access is provided. The first method includes the steps of (1) storing information associated with commands that are to be...
7516262 Data transfer apparatus with control of buses to enable reading of predetermined data sizes  
A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus...
7516258 Electronic apparatus and control method  
An electronic apparatus includes a memory, first and second bus masters, a counting unit and a control unit. The first and second bus masters are capable of accessing the memory. The counting unit...
7490184 Systems and methods for data intervention for out-of-order castouts  
Systems and methods for data intervention for out-of-order castouts are disclosed. Embodiments provide for transmitting snoopable requests received from one or more requesting devices to one or...
7484046 Reducing number of rejected snoop requests by extending time to respond to snoop request  
A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address,...
7484017 Dequeuing from a host adapter two-dimensional queue  
A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is...
7480754 Assignment of queue execution modes using tag values  
The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment a tag is assigned for each of several disc access commands sent by the host....
7478190 Microarchitectural wire management for performance and power in partitioned architectures  
A method for utilizing heterogeneous interconnects comprising wires of varying latency, bandwidth and energy characteristics to improve performance and reduce energy consumption by dynamically...
7475173 Integrated disc drive controller  
An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated...
7461190 Non-blocking address switch with shallow per agent queues  
In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage...
7451258 Rotating priority queue manager  
The present invention is a rotating priority queue manager. A rotating priority queue manager in accordance with the present invention may include a plurality of source data channels, a...
7424562 Intelligent PCI bridging consisting of prefetching data based upon descriptor data  
A bridging device has at least two ports. The first port allows the device to communicate with devices on an expansion bus and at least one other port to allow the bridge to communicate with a...
7421545 Method and apparatus for multiple sequence access to single entry queue  
Bus address, function and system information in relation to bus requests are maintained in a centralized location ( 702 ). Parallel access to the centralized data is facilitated through the use of...
7406554 Queue circuit and method for memory arbitration employing same  
A memory access arbitration scheme is provided where transactions to a shared memory are stored in an arbitration queue. A collapsible queuing structure and method are provided, such that once a...
7401126 Transaction switch and network interface adapter incorporating same  
A transaction switch and integrated circuit incorporating said for switching data through a shared memory between a plurality of data interfaces that support different data protocols, namely...
7386750 Reduced bus turnaround time in a multiprocessor architecture  
Systems and methods of reducing bus turnaround time in a multiprocessor architecture are disclosed. An exemplary method may include mastering the system bus within one idle bus clock cycle of a bus...
7373445 Method and apparatus for allocating bus access rights in multimaster bus systems  
A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from...
RE40317 System for receiving a control signal from a device for selecting its associated clock signal for controlling the transferring of information via a buffer  
A computer system including a first component operated in response to the timing of a first clock, apparatus for storing information, apparatus for transferring information from the first component...
7360009 Data transfer apparatus for limiting read data by a bus bridge with relay information  
A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus...
7328300 Method and system for keeping two independent busses coherent  
Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a...
7308510 Method and apparatus for avoiding live-lock in a multinode system  
A reordering priority to grant higher priority for a request over a response when a predetermined condition is detected for live-lock prevention is discussed. Specifically. A a circuit and...
7302684 Systems and methods for managing a run queue  
Various implementations of the described subject associate a plurality of threads that are sorted based on thread priority with a run queue in a deterministic amount of time. The run queue includes...
7290065 Method, system and product for serializing hardware reset requests in a software communication request queue  
A system, method, and product are disclosed in a data processing system for serializing hardware reset requests in a software communication request queue in a processor card. The processor card...
7277975 Methods and apparatuses for decoupling a request from one or more solicited responses  
Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Translation logic couples to the...
7251723 Fault resilient booting for multiprocessor system using appliance server management  
A multiprocessor computer system implements fault resilient booting by using appliance server management. While previous systems have utilized fault resilient booting, it has required the use of a...
7251702 Network controller and method of controlling transmitting and receiving buffers of the same  
In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from...
7209988 Management of the freezing of a functional module in a system on a chip  
An electronic system comprises an initiator module and a target module addressable by the initiator module. The initiator module is activated by edges of an activation signal generated from a first...
7185137 Bus bridge with stored controlling relay information  
A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus...
7174402 Systems, network devices and methods for highly configurable peer-to-peer communications between network devices communicating via a common bus  
A system and method are provided for initiating peer-to-peer communications via a network bus. The system includes a bus controller in electrical communication with the network bus for controlling...
7155554 Methods and apparatuses for generating a single request for block transactions over a communication fabric  
Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communications fabric. A first functional block...
7143224 Smart card for performing advance operations to enhance performance and related system, integrated circuit, and methods  
An integrated circuit for a smart card may include a transceiver and a controller for cooperating with the transceiver to receive operating requests from a host device. The controller may perform...
7139884 Method, apparatus and computer program product for implementing enhanced autonomic backup using multiple backup devices  
A method, apparatus and computer program product are provided for implementing enhanced autonomic data backup using multiple backup devices. A media definition object is defined for saving...
7139881 Semiconductor device comprising a plurality of memory structures  
A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing...
7124231 Split transaction reordering circuit  
The present invention provides a technique for ordering responses received over a split transaction bus, such as a HyperTransport bus (HPT). When multiple non-posted requests are sequentially...
7117308 Hypertransport data path protocol  
A data path protocol eliminates most of the conventional read transactions required to transfer data between devices interconnected by a split transaction bus, such as a HyperTransport (HPT) bus....
7099972 Preemptive round robin arbiter  
A resource allocation arbitration system. The system includes a plurality of storage devices, a plurality of indicators, and a plurality of mask bits. Each storage device stores requests for...
7096307 Shared write buffer in a peripheral interface and method of operating  
A data processing system has a single configurable write buffer within a peripheral interface unit that is shared among multiple peripherals. Configuration registers are dynamically programmed to...
7096290 On-chip high speed data interface  
An integrated circuit chip, particularly a southbridge, is provided that has a first and a second circuit unit. Each circuit unit can send requests to the other one and send back a response when...
7085869 Arrangement for managing transmitted packets requiring acknowledgement in a host channel adapter  
A host channel adapter configured for outputting packets, according to a service protocol requiring acknowledgement messages within a prescribed time interval following transmission, utilizes a...
7080174 System and method for managing input/output requests using a fairness throttle  
A system and method for providing a desired degree of fairness of access to data transfer resources by a plurality of command-initiating bus agents. A bus arbiter allocates general ownership of the...
7055012 Latency reduction using negative clock edge and read flags  
A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have...
7043612 Compute node to mesh interface for highly scalable parallel processing system and method of exchanging data  
An interface circuit for interfacing one or more compute nodes to a mesh and for serving a wide range of MPP systems and a method for exchanging data between a first agent on an expansion bus and a...
Matches 1 - 50 out of 258 1 2 3 4 5 6 >