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7631130 Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor  
A circuit for selecting one of N requestors in a round-robin fashion is disclosed. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed...
7631131 Priority control in resource allocation for low request rate, latency-sensitive units  
A mechanism for priority control in resource allocation for low request rate, latency-sensitive units is provided. With this mechanism, when a unit makes a request to a token manager, the unit...
7610421 Bus request control circuit  
A bus request control circuit provided in a signal processing circuit having a higher priority in an arbitration circuit includes a request signal transmitting section which transmits a request...
7539806 Arbitrator and its arbitration method  
The present invention provides an arbiter and its arbitration method. The master devices in the bus system can be divided into primary master devices and secondary master devices. Said arbiter has...
7512729 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency  
A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes...
7509447 Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor  
An apparatus for selecting one of N requestors of a shared resource in a round-robin fashion is disclosed. One or more of the N requestors may be disabled from being selected in a selection cycle....
7457886 System and method for input/output scheduling  
A system and method for Input/Output scheduling are described herein. In one embodiment, the method includes installing a plurality of Input/Output (I/O) schedulers to schedule I/O requests for a...
7451258 Rotating priority queue manager  
The present invention is a rotating priority queue manager. A rotating priority queue manager in accordance with the present invention may include a plurality of source data channels, a...
7428607 Apparatus and method for arbitrating heterogeneous agents in on-chip busses  
A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and...
7385965 Multiprocessor control block for use in a communication switch and method therefore  
A communication switch that includes a multiprocessor control block and a method therefore is presented. The multiprocessor control block includes a centralized resource and routing processor that...
7350002 Round-robin bus protocol  
A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During...
7325082 System and method for guaranteeing transactional fairness among multiple requesters  
A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is...
7305507 Multi-stage round robin arbitration system  
Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is...
7302510 Fair hierarchical arbiter  
A fair hierarchical arbiter comprises a number of arbitration mechanisms, each arbitration mechanism forwarding winning requests from requestors in round robin order by requestor. In addition to...
7260688 Method and apparatus for controlling access to memory circuitry  
Method and apparatus for controlling access to memory circuitry is described. In one example, access to the memory circuitry is controlled among a plurality of bus interfaces of a data processing...
7254674 Distribution of I/O requests across multiple disk units  
A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group...
7240135 Method of balancing work load with prioritized tasks across a multitude of communication ports  
A processor is used to evaluate information regarding the number, size, and priority level of data transfer requests sent to a plurality of communication ports. Additional information regarding the...
7225280 Portable device for one-on-one transfer between another such device wherein device is restricted to data storage and transfer with single interface for data exchange  
A device, a method and a system for portable data storage and transfer through a simplified device interface. The operations of the device are restricted, in order to increase the ease of use of...
7209992 Graphics display system with unified memory architecture  
A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and...
7197577 Autonomic input/output scheduler selector  
The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped...
7181547 Identifying nodes in a ring network  
A master node in a packet ring network periodically sends a packet containing a discovery marker into the packet ring network. As each node in turn receives the packet, each adds its own discovery...
7181558 Avoidance of extended bus occupancy through simple control operation  
A shared bus system includes a bus, a first circuit which accesses the bus, a second circuit which shares the bus with the first circuit, and accesses the bus, a counter circuit which is provided...
7158046 System and method for radio frequency tag group select  
A master entity is capable of broadcasting commands to slaves which move to another state when they satisfy a primitive condition specified in the command. By moving slaves among three sets, a...
7143220 Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies  
A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and...
7143219 Multilevel fair priority round robin arbiter  
A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each...
7130942 Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding  
A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor...
7127540 Apparatus and method for controlling frequency of bus use  
In a bus arbitration method and bus arbiter which simultaneously considers fairness and priority and enables fairness and priority to be readjusted by a program, that is, by software, arbitration...
7120714 High-speed starvation-free arbiter system, rotating-priority arbiter, and two stage arbitration method  
A two-stage arbiter system comprises a first-stage arbiter to grant a request to one of a plurality of requestors in accordance with a first arbitration scheme and a second-stage arbiter to grant...
7111098 Information processing apparatus, information processing method, recording medium and program  
A bus arbitration system employs counters respectively provided for an encoding section and an decoding section that are started when there is a request signal from the respective encoding section...
7073003 Programmable fixed priority and round robin arbiter for providing high-speed arbitration and bus control method therein  
In a programmable fixed priority and round-robin arbiter and a bus control method of the same, the arbiter includes, an HPRIF rotating unit, a request-reordering unit, a request-selecting unit, and...
7051133 Arbitration circuit and data processing system  
An arbitration circuit and a data processing system which ensure fair bus access are provided. An arbitration circuit ( 1 ) has a priority check block ( 21 ) and a round robin block ( 22 ). The...
7047335 Method for receiving user defined frame information structure (FIS) types in a serial-ATA (SATA) system  
An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user...
7007123 Binary tree arbitration system and method using embedded logic structure for controlling flag direction in multi-level arbiter node  
A binary-tree-based arbitration system and methodology with attributes that approximate a Generalized Processor Sharing (GPS) scheme for rendering fairer service grants in an environment having a...
6996647 Token swapping for hot spot management  
A method and apparatus are provided for efficiently managing hot spots in a resource managed computer system. The system utilizes a controller, a series of requestor groups, and a series of loan...
6965923 System and method for assigning addresses to memory devices  
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing...
6895459 Bus arbitration method employing a table of slots suitably distributed amongst bus masters  
A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are...
6862639 Computer system including a receiver interface circuit with a scatter pointer queue and related methods  
A computer system may include a processor, at least one memory coupled to the processor and having a plurality of scattered memory locations each having a pointer associated therewith, and a...
6812852 System and method for selecting a subset of autonomous and independent slave entities  
A master entity is capable of broadcasting commands to a plurality of three-state-selection machine slaves. Transitions from one state to another are effected on instruction from commands in a...
6771556 Single port random access memory equipped with a relief module to operate as a dual port shared memory  
The present relief module equipped random access memory avoids the need for enforced idle cycles for the processors, thereby enabling the State Machine to operate at its maximum speed. This relief...
6769043 Ensuring fair access to upstream trunk bandwidth in ATM subtended configurations  
To ensure fair access to upstream trunk bandwidth among a plurality of interface units, a plurality of queues is provided in a first unit. One of the queues is associated with the first interface...
6728792 Priority queue with arbitrary queuing criteria  
A method in a computing system ( 100 ) includes the steps of enqueuing items in a functional queue prioritized according to sort criteria ( 132 ), modifying the sort criteria ( 132 ) while the...
6714997 Method and means for enhanced interpretive instruction execution for a new integrated communications adapter using a queued direct input-output device  
Method and means to provide a mechanism by which a hypervisor can permit a real machine to interpretively execute certain I/O instructions independently of the value of an I-bit in the subchannel....
6715042 Systems and methods for multiport memory access in a multimaster environment  
A multiprocessor digital amplifier system is disclosed. A first processor is configured to decode a digital signal from a digital signal source. A second processor configured to provide control...
RE38388 Method and apparatus for performing deferred transactions  
A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus...
6678771 Method of adjusting an access sequencing scheme for a number of PCI- compliant units coupled to a PCI bus system  
A method of adjusting an access sequencing scheme for a number of PCI (Peripheral Component Interconnect) compliant units coupled to a PCI bus system on a computer system. These PCI-compliant units...
6678774 Shared resource arbitration method and apparatus  
An arbiter apparatus for selecting an agent to use a shared resource such as memory. A normal round robin list is utilized in the selection process during boot operation. During the initialization...
6675245 Apparatus and method for providing round-robin arbitration  
The present invention provides round-robin arbitration between requests for access to a shared resource such as a data bus ( 7 ), shared by a plurality of hardware modules. A central counter ( 1 )...
6654834 Method and apparatus for data transfer employing closed loop of memory nodes  
Data transfer between a master node ( 300 ) and plural memory nodes ( 301-308 ) follows a synchronous fixed latency loop bus ( 255 ). Each memory node includes bus interface ( 311-318 ) which...
6647449 System, method and circuit for performing round robin arbitration  
A method, system and circuit for performing a round robin arbitration, which includes an input operable to receive a plurality of requests, a conditional request masking logic to selectively send...
6633926 DMA transfer device capable of high-speed consecutive access to pages in a memory  
A DMA transfer device transfers data from a first region to a second region in a memory allowing high-speed page access. The DMA transfer device includes: a first detecting unit for detecting a...
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