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6801972 |
Interface shutdown mode for a data bus slave
A slave device receives commands from a master device for execution on a first-in, first-out basis. A status register is responsive to a queue of commands to provide a COMMAND_STATUS_FULL signal...
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6799234 |
Apparatus and method for randomly assigning slots in a PCI backplane
A system and method for automatically assigning resources to a slave device inserted into a PCI backplane utilizes pairs of PCI GNT/REQ lines as bus lines of a time division multiplexed multiplexer...
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6799235 |
Daisy chain latency reduction
Transmitting data on a serial data transmission path to reduce latency including reading only enough of a device address of a serial data word to determine if the serial data word is addressed to a...
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6799233 |
Generalized I2C slave transmitter/receiver state machine
A robust state machine is provided for controlling a slave interface to an I 2 C-bus. The state machine is configured to enforce the slave-device-protocol of the I 2 C specification, and to provide...
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6785755 |
Grant removal via dummy master arbitration
A system for controlling arbitration that may be used for a bus. The system generally comprises a bus, at least one master, and a first circuit coupled between the bus an the at least one master....
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6782439 |
Bus system and execution scheduling method for access commands thereof
A bus system and execution scheduling method used for the bus system are provided. The execution scheduling method used for the bus system includes the steps of (a) transmitting one or more access...
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6772254 |
Multi-master computer system with overlapped read and write operations and scalable address pipelining
A multi-master computer system having overlapped read and write signal with scalable address pipelining programmable increases the depth of address pipelining independently on two overlapped read...
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6769035 |
Same single board computer system operable as a system master and a bus target
A same single board computer system that is operable as a system master and a bus target and methods of operating the same are described. In one system, a processor having a system master mode of...
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6745254 |
Programmable logic controller method, system and apparatus
A programmable logic controller with enhanced and extended the capabilities. A digital input filter implement filters with considerable less logic by simulating the action of a capacitor being...
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6738844 |
Implementing termination with a default signal on a bus line
Implementing termination on a bus. According to one embodiment of the present invention a driver drives a default signal on to a line, then drives an information signal on to the line, and then...
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6738845 |
Bus architecture and shared bus arbitration method for a communication device
A multiple bus architecture includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are...
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6735653 |
Bus bandwidth consumption profiler
A bus bandwidth consumption profiler for measuring and reporting bus cycle utilization in a system having multiple bus masters, including master counters paired with the masters to count cycles of...
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6732301 |
Serial bus diagnostic port of a digital system
A digital system provides a serial bus diagnostic port such as, for example, a universal serial bus (USB) diagnostic port. The USB diagnostic port can include a USB slave device operable to...
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6732217 |
Control and supervisory signal transmission system
A parent station output section changes a duty ratio between a period of a level other than a predetermined power-supply voltage level and a subsequent period of the power-supply voltage level...
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6728618 |
Method for activating a system for controlling and/or regulating operational sequences in a motor vehicle having several equal-access control units
A system for controlling and/or regulating operational sequences in a motor vehicle having several equal-access control units for controlling and/or regulating certain functions in the motor...
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6728808 |
Mechanism for optimizing transaction retries within a system utilizing a PCI bus architecture
A mechanism for optimizing transaction retries within a system utilizing a peripheral component interconnect (PCI) bus architecture. Specifically, one embodiment of the present invention includes a...
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6725306 |
DEBUG mode for a data bus
A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a...
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6725313 |
Communications system and method with multilevel connection identification
A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a...
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6725307 |
Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch,...
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6718488 |
Method and system for responding to a failed bus operation in an information processing system
In an information processing system, a failed bus operation is detected. In response to the detecting, a primary power plan is cycled in the information processing system.
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6715049 |
Microcomputer and information processing system
A microcomputer and an information processing system protect data stored therein and secure the safety of the data. The microcomputer ( 1 ) has a memory ( 3 ), a read protect register ( 13 ), and a...
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6708246 |
Signal processing device with bus ownership control function
A signal processing device includes an integrated processor, a video processing unit coding a video signal, and an interface controlling a bus ownership between the integrated processor and an...
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6693678 |
Data bus driver having first and second operating modes for coupling data to the bus at first and second rates
Information is coupled to a data bus such as an I 2 C data bus using a push-pull circuit. The push-pull circuit provides for communicating on the data bus at two different data rates. The push-pull...
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RE38428 |
Bus transaction reordering in a computer system having unordered slaves
A mechanism is provided for reordering bus transactions to increase bus utilization in a computer system in which a split-transaction bus is bridged to a single-envelope bus. In one embodiment,...
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6684279 |
Method, apparatus, and computer program product for controlling data transfer
A method, apparatus, and computer program product are described for controlling data transfer. A next data packet to be transferred is retrieved. A determination is made regarding whether a data...
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6678781 |
Network configuration method
A network configuration method ensuring high reliability of bridge manager selection and bus reset is disclosed. After configuring each of the IEEE 1394 buses according to IEEE 1394 standard, a...
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6678770 |
PCI bus control system having intelligent devices that own and manage non-intelligent devices for relaying information from non-intelligent devices
In a peripheral component interconnect (PCI) bus system in which both intelligent and non-intelligent devices are connected to the PCI bus, each non-intelligent device is owned and managed by an...
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6665306 |
Immediate cut-off protocol and interface for a packet-based bus connecting processors
A bus interface and method allow a special purpose processor and other components on a bus to efficiently communicate with a network controller. The interface and protocol support a variety of...
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6665748 |
Specialized PCMCIA host adapter for use with low cost microprocessors
Apparatus and method for providing DMA transfers between an adapter card with or with out DMA capabilities and a system CPU with DMA capabilities. An adapter DMA controller circuit resides between...
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6665757 |
Communication interface having a master activating/deactivating a first signal with a clock signal after a predetermined time after a slave activating/deactivating the first signal
A communication interface of the present invention includes a clock signal line, a first signal line, a second signal line and one or more data signal lines as communication signal lines between a...
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6662306 |
Fast forwarding slave requests in a packet-switched computer system by transmitting request to slave in advance to avoid arbitration delay when system controller validates request
A method and apparatus for packet-switched flow control of transaction requests in uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and...
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6662251 |
Selective targeting of transactions to devices on a shared bus
A system in which bus signals are selectively modified to effectively isolate desired bus agents from the bus. The selective modification of bus signals may be determined from a stored table...
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6654821 |
Remotely controllable electronic apparatus and remote control method
A method and system for coordinating control of a remotely controllable electronic apparatus by a first and second control apparatus that use different standards to control the remotely...
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6654835 |
High bandwidth data transfer employing a multi-mode, shared line buffer
A technique for transferring data between a first device and a second device using a shared line buffer connected to a system bus which couples the first device and the second device. The technique...
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6654836 |
Dual master device for improved utilization of a processor local bus
A dual master apparatus for mastering a Processor Local Bus (PLB), which is a high-performance, on-chip bus used in many System on Chip (SOC) applications, supporting up to 16 masters. The...
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6629204 |
Disk array controller including a plurality of access paths
The disk array controller includes a plurality of interfaces with respective processors for connecting with a host computer or disk devices, duplicated shared memories connected in a one to one...
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6611722 |
Control and data transmission installation and a process for the transmission of safety-related data
A control and data transmission installation and a process for transmission of safely-related data in a control and data transmission installation. In accordance with the invention, safety...
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6609168 |
Bus master read request adaptive prefetch prediction method and apparatus
An apparatus and method for predicting quantities of data required by requesting devices capable of requesting unspecified quantities of data from storage device, in which prediction of quantities...
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6604159 |
Data release to reduce latency in on-chip system bus
An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking transactions on...
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6598104 |
Smart retry system that reduces wasted bus transactions associated with master retries
The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart...
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6591321 |
Multiprocessor system bus protocol with group addresses, responses, and priorities
A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are...
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6591322 |
Method and apparatus for connecting single master devices to a multimaster wired-and bus environment
A “firewall” apparatus is placed between a single bus master device and a multimaster I 2 C bus system. The firewall apparatus transforms all multimaster bus errors into simple NAK errors and...
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6591294 |
Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
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6587813 |
PCI bus system testing and verification apparatus and method
An improved PCI verification method and apparatus provides iterative testing of all desired conditions or protocol combinations in a PCI system. One or more commands may be tested in combination...
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6587905 |
Dynamic data bus allocation
A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master...
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6586968 |
Programmable bit ordering for serial port
An order in which bits for serial data are transmitted or received by a first device, integrated circuit (IC) or logic, is programmable to be either from most significant bit (MSB) to least...
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6581117 |
Device and a method for the automatic control and administration of medical apparatus and installations
The automatic control and administration of program-controlled endoscopic apparatuses allocated to an operation within an operating theater belonging to a clinic region and connected amongst one...
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6581116 |
Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system
A method for transmitting ordered packets on a bus within a data processing system is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. The bus...
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6578098 |
Predictive mechanism for ASB slave responses
The present invention is drawn to a computer implemented method and system for synchronously driving slave responses onto an ASB (advanced system bus) bus. On the one hand, in response to a read...
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6578097 |
Method and apparatus for transmitting registered data onto a PCI bus
A method and apparatus for transmitting registered data onto a PCI bus is provided, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit...
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