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6959351 |
Handling of a multi-access instruction in a data processing apparatus
The present invention provides a data processing apparatus and method for handling a multi-access instruction of the type which specifies that an access request of a first type and an access...
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6952618 |
Input/output control systems and methods having a plurality of master and slave controllers
Apparatus and methods for controlling a system that operates responsive to a plurality of input control signals are disclosed. During operation the system generates a plurality of output...
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6952747 |
Method of delaying bus request signals to arbitrate for bus use and system therefor
In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the...
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6948018 |
Method and system for exchanging data
A method and a system exchange data between a program-controlled device, in particular a microcontroller, and a logic circuit. A control signal is transmitted from the program-controlled device to...
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6944697 |
Serial device daisy chaining method and apparatus
A method includes the step of serially clocking a mask value through a plurality of subscriber line interface circuits (SLICs) until each SLIC stores a corresponding portion of the mask value, and...
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6944695 |
Method and apparatus for connecting devices to a bus
A two-wire serial (TWS) bus allows bus mastering by any device on the bus utilizing pull-ups. The bus is actively driven low, but typically pulled high by pull-up resistors for each device on the...
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6938113 |
Apparatus for flushing slave transactions from resetting masters of a data bus
When a master device resets, flush commands are issued to a flush master register in the slave devices. A comparator compares the identification of the master device associated with the flush...
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6934786 |
Server chassis hardware master system and method
A system and method for selecting a hardware master from a plurality of computing devices and controlling the communication of a master control signal(s) to one or more of the plurality of...
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6931470 |
Dual access serial peripheral interface
A dual access peripheral interface uses a shared data bus ( 16 ) for communication with dual master units ( 30,32 ) coupled to a common peripheral device ( 34 ). Each master control unit provides a...
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6928505 |
USB device controller
A device controller for connecting a function engine that supports an application to a packet-switched serial bus to which a host device is connected. The interface device includes a serial...
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6922790 |
Three wire communication protocol
Disclosed is a serial communications protocol for connecting a master and a plurality of slaves using three communication lines. The protocol establishes a method for communication between the...
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6912606 |
Generic serial bus architecture
A serial bus is provided that supports multiple data transmission protocols. The serial bus allows a bus master to communicate with a variety of semiconductor devices that support a variety of...
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6912609 |
Four-phase handshake arbitration
A four-phase arbitration system employs a master and a slave arbiter. The master arbiter operates to provide ownership of a bus to a first device if a second device, coupled to the slave arbiter is...
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6912016 |
Audiovisual system formed by various appliances of which certain appliances are formed by various functionality modules
Various appliances linked up by a bus that can transmit video data form the system, and functionality modules themselves connected to the bus form certain appliances. A command enables to select...
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6910086 |
Controller device, communication system and controlling method for transmitting reserve commands from a controller to target devices
Disclosed herein are a controller device, a communication system and a controlling method for transmitting commands for designating two modes used in a setup comprising a controller device and a...
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6909307 |
Bidirectional bus driver and bidirectional bus circuit
A bidirectional bus driver includes a first buffer which supplies the data signal to the second bus when the first control signal is enabled; a second buffer which supplies the data signal to the...
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6910087 |
Dynamic command buffer for a slave device on a data bus
A slave device includes a command FIFO that stores commands for a device controller on a first-in, first-out basis to execute a read or write transaction. Commands are received from the data bus by...
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6907331 |
Vehicle control system and apparatus therefor
The present invention relates to a method and apparatus for a vehicle control system comprising electronic modules used for the automatic control of vehicle operation. The method for automatic...
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6907492 |
Interface circuit which meets universal serial bus standard and performs host and device functions
When a device such as a printer is connected to a connector 49 via a USB cable using an electronic device 40 as a host, a selecting circuit 43 b is switched to a host function circuit 43 a ...
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6907488 |
Serial data transmission via a bus system
The present invention relates to a passive component for a bus system, such as, for example, a field bus system, having a bus interface for connection to a bus, a serial interface for serially...
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6895458 |
Opcode to turn around a bi-directional bus
A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data...
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6889310 |
Multithreaded data/context flow processing architecture
Multithreaded data- and context-flow processing is achieved by flowing data and context (thread) identification tokens through specialized cores (functional blocks, intellectual property). Each...
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6886064 |
Computer system serialization control method involving unlocking global lock of one partition, after completion of machine check analysis regardless of state of other partition locks
In a computer system having a logical-partitioned server, each partition of the server is provided with its own separate lock and access corridor, in addition to a global lock. When the locking of...
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6883051 |
Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses
In one embodiment of the present invention, a slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave devices...
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6880036 |
Apparatus for receiving audiovisual programs
The present invention relates to an apparatus for receiving audio-visual programs comprising a circuit for communication with means of connection to a bi-directional communication network, wherein...
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6874052 |
Expansion bridge apparatus and method for an I2C bus
The present invention is an I 2 C (inter-IC control) bridge device which implements a communication protocol layered on top of a standard I 2 C protocol. The layered protocol used by the bridge...
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6874044 |
Flash drive/reader with serial-port controller and flash-memory controller mastering a second RAM-buffer bus parallel to a CPU bus
A flash-drive or flash-card reader connects to a personal computer (PC) through a serial link such as a Universal-Serial-Bus (USB), IEEE 1394, SATA, or IDE. A local CPU acts as the bus master of a...
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6871250 |
Data bus, particularly in motor vehicles
The invention relates to a data bus comprising slave nodes executing functions based on addressed command telegrams of an electronic main control unit which is also connected to said data bus. The...
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6868459 |
Methods and structure for transfer of burst transactions having unspecified length
Methods and associated structure for providing a substitute, predetermined, fixed length when transferring burst transactions from one device to another through a bridge device where the burst...
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6862266 |
Loop test apparatus of packet routing bus in communication system and loop test method
A loop test apparatus of a packet routing bus in a communication system and a loop test method thereof capable of testing entire functions of the packet routing bus of a full-duplex transmission...
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6859668 |
Structured system for monitoring and controlling the engineering equipment of an installation
The present inventions pertains to the field of automatic control systems based on computer technology, and essentially relates to a structured system for monitoring and controlling the engineering...
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6857029 |
Scalable on-chip bus performance monitoring synchronization mechanism and method of use
A bus performance monitoring mechanism for systems on a chip (SOC) is disclosed. The system comprises a muxing logic adapted to be coupled to a plurality of master devices, a plurality of slave...
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6856420 |
System and method for transferring data within a printer
A printer is described. The printer includes a CPU, a DMA controller and an internal memory. The CPU and the DMA controller are each connected to a first memory bus. The internal memory is...
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6857035 |
Methods and apparatus for bus mastering and arbitration
Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system....
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6854030 |
Integrated circuit device having a capacitive coupling element
An integrated circuit memory device that include an input receiver, an output driver, and a capacitive coupling element. The capacitive coupling element includes a first capacitor electrode and a...
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6851004 |
Adaptive retry mechanism
An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency...
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6850998 |
Disk array system and a method for controlling the disk array system
In a disk array system of the present invention, each host or disk interface unit is connected to each shared memory unit through a switch unit. The switch unit includes the number of packet...
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6851056 |
Control function employing a requesting master id and a data address to qualify data access within an integrated system
An access control function for an integrated system is provided which determines data access based on the master id of a requesting master within the system and the address of the data. The access...
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6842808 |
Data exchange between users connected by a bus system and having separate time bases
A method and device for the exchange of data in messages between at least two users which are connected by a bus system and have separate time bases, the messages containing the data being...
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6842669 |
Component interface module
A component interface module (CIM) arbitrates through priority logic component command signals from redundant systems and integrates the selected priority command signal with component feedback...
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6842806 |
Method and apparatus for interconnecting wired-AND buses
One or more bus bridges are used to partition a large I 2 C bus into smaller bus segments. By programming address bitmaps that are internal to each bridge, the various bus segments can be made to...
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6834318 |
Bidirectional bus repeater for communications on a chip
A bidirectional bus repeater is disclosed that connects individual segments of a bidirectional bus. The exemplary bidirectional bus repeater consists of a direction control block and a buffer...
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6826632 |
System for identifying the interconnection of peripheral devices
A system and method for identifying the interconnection of peripheral devices in an information handling system and generating a model of the interconnection of the devices is disclosed. The system...
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6823411 |
N-way psuedo cross-bar having an arbitration feature using discrete processor local busses
A bus architecture is provided to facilitate communication between independent bus masters and independent bus slaves by having two or more bus arbiters in a system-on-chip (SOC) system. Each bus...
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6820150 |
Method and apparatus for providing quality-of-service delivery facilities over a bus
The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an...
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6816931 |
Upstream peripheral device serving as a USB host
A scanner, which can be a USB host, includes a hub, a scanner component, a virtual printer component and an internal host. The hub is connected to a computer host and the scanner. The scanner...
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6816925 |
Combination personal data assistant and personal computing device with master slave input output
In order to provide continuous communication ability in a computer architecture that integrates a computer (PC) architecture system and a personal digital assistant (PDA) architecture system, a...
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6812852 |
System and method for selecting a subset of autonomous and independent slave entities
A master entity is capable of broadcasting commands to a plurality of three-state-selection machine slaves. Transitions from one state to another are effected on instruction from commands in a...
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6813527 |
High integrity control system architecture using digital computing platforms with rapid recovery
A control system architecture suitably includes sufficient computation redundancy and control command management to isolate and recover a faulted processor and/or to recover all processing units in...
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6813664 |
System transmitting data in equidistance cycles using successive synchronization signals for detecting and signaling access violations
A user terminal ( 1 ) having a communications processor ( 10 ) that carries out a cyclic data transmission. During a cyclic part (ZYK,x) of a cycle (Z,x) in which user data are transmitted, a DP...
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