Matches 601 - 650 out of 654 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 >
Match Document Document Title
5327121 Three line communications method and apparatus  
A communications scheme is provided whereby each of a plurality of I/O devices is connected to a system controller via three lines: a bidirectional data bus, a clock bus, and a bidirectional...
5327540 Method and apparatus for decoding bus master arbitration levels to optimize memory transfers  
A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a...
5321818 System for arbitrating for access on VME bus structures  
System for providing self-selection arbitration among a plurality of slave processors connected to a VME back plane. The slave processors are connected to a common ID bus, interrupt line, and...
5309567 Structure and method for an asynchronous communication protocol between master and slave processors  
In accordance with the present invention, a structure and a method for asynchronously interfacing a master processor and a slave processor is provided by receiving from and providing to the master...
5305442 Generalized hierarchical architecture for bus adapters  
A top state controller controls a bus adapter to a selected master or slave top state in response to a command on a local or system bus during a dispatch state of the bus adapter. The bus adapter...
5305443 Microprocessor with low power bus  
A microprocessor provides a bus state referred to as "loop-back". This state holds the data bus at valid logic levels, without use of resistors, after a read transaction has been completed and...
5299315 Personal computer with programmable threshold FIFO registers for data transfer  
This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small...
5297292 Bus system wherein a bus-using request signal is issued in advance of a determination that a bus is to be used and is thereafter cancelled if the bus is not used  
A method is provided for controlling bus-using rights in a multi-bus system which has a plurality of buses and a plurality of units connected to each of the buses. A unit connected to one bus is...
5287520 Monitor system having list of items with fixed time slices for transmitting timing signals at the end of a communication between master processor and slave processors  
A system for measuring a plurality of parameters comprises a master processor and a multiplicity of slave processors. The master processor operates in time slices of 2 ms. Communication with the...
5278959 Processor usable as a bus master or a bus slave  
A processor specially adapted for use as a coprocessor The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which...
5263172 Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals  
A computer system which includes a synchronous digital, multibit system bus having a clock path, a master speed indicator path and a slave speed indicator path, a bus control circuit which provides...
5257356 Method of reducing wasted bus bandwidth due to slow responding slaves in a multiprocessor computer system  
In a multiprocessor computer system, wasted bus bandwidth resulting from slow responding slaves is reduced by relinquishing the master that was busied by the slow responding slave, and then causing...
5237676 High speed data transfer system which adjusts data transfer speed in response to indicated transfer speed capability of connected device  
A computer system bus includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both devices support such a transfer, a high speed bus...
5214644 Electronic device with data transmission function  
An electronic device for transmitting data to an audio visual device in a domestic data communications network system includes a communications arrangement for transferring a memory access...
5199106 Input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the bus  
In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected...
5195186 Condition connection for a parallel component processor and method  
A system and method by which individual processors in a parallel component processor can flexibly communicate a variety of global conditions via a single open collector status line is disclosed.
5193159 Microprocessor system  
When a coprocessor communicates a plurality of data items with a master processor and a memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein...
5131085 High performance shared main storage interface  
A high performance interface joins multiple processing devices configured as masters, with multiple memory cards or other devices configured as slaves. The interface includes a working data bus for...
5062044 Temporary bus master for use in a digital system having asynchronously communicating sub-systems  
A circuit embodied in a single integrated circuit, which is connected through an asynchronous communication bus to a primary bus master and a permanent bus slave, cooperates with the master and...
5056000 Synchronized parallel processing with shared memory  
A high speed computer that permits the partitioning of a single computer program into smaller concurrent processes running in different parallel processors. The program execution time is divided...
5043877 Architecture converter for slave elements  
An apparatus for transferring data between a computer system having a first architecture and a slave element having a second architecture. The apparatus includes a first connector corresponding to...
4990907 Method and apparatus for data transfer  
A bus master and a plurality of bus slaves are connected through a data bus and a control bus, and data transfer of hand shake system is performed. In the control bus, at least data strobe signal...
4949241 Microcomputer system including a master processor and a slave processor synchronized by three control lines  
A microcomputer system includes a master processor and a coprocessor interconnected via a bus. The coprocessor supplies first, second and third signals to the master process, the first (BUSY)...
4942519 Coprocessor having a slave processor capable of checking address mapping  
A coprocessor device having a virtual storage system comprises a master microprocessor, a slave microprocessor controlled by the master microprocessor to execute an operation designated by...
4935868 Multiple port bus interface controller with slave bus  
A new integrated circuit for interfacing a standard IEEE 796 bus to a VSB-type buffer bus. This integrated circuit includes a DMA channel for high speed access of the IEEE 796 bus to the buffer...
4926318 Micro processor capable of being connected with a coprocessor  
A micro processor capable of being connected with a coprocessor is disclosed. The microprocessor includes an execution unit and a bus control unit coupled to the execution unit. When the execution...
4912633 Hierarchical multiple bus computer architecture  
A modular and hierarchical multiple bus computer architecture in which the master bus and slave bus are substantially identical, and communicate through a combination of an interface controller and...
4894768 Data processing system with coprocessor  
When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus...
4876643 Parallel searching system having a master processor for controlling plural slave processors for independently processing respective search requests  
A parallel processing search system for searching and updating a database at the request of a host system, including a master processor connected to a host system bus for transfer of information...
4860191 Coprocessor with dataflow circuitry controlling sequencing to execution unit of data received in tokens from master processor  
An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific...
4821231 Method and apparatus for selectively evaluating an effective address for a coprocessor  
A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format,...
4817037 Data processing system with overlap bus cycle operations  
A data processing system including several devices connected to an asynchronous communications bus for communications between these devices. The communications bus includes a protocol that requires...
4816997 Bus master having selective burst deferral  
A data processing system having a bus master, a cache, and a memory which is capable of transferring operands in bursts in response to a burst request signal provided by the bus master. The bus...
4774625 Multiprocessor system with daisy-chained processor selection  
A multiprocessor system includes a priority discriminator which passes a request signal from a master operation processing unit serially through a plurality of slave operation processing units in...
4750110 Method and apparatus for executing an instruction contingent upon a condition present in another data processor  
A system for interfacing a Processor to a Coprocessor using standard bus cycles. The processor, upon encountering in its instruction stream an instruction having a particular Operation word format,...
4736319 Interrupt mechanism for multiprocessing system having a plurality of interrupt lines in both a global bus and cell buses  
A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A...
4731736 Method and apparatus for coordinating execution of an instruction by a selected coprocessor  
A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format,...
4654784 Circuit arrangement for routing signals between a master-slave pair of controlling processors and several master-slave pairs of controlled processing units  
A plurality of switching modules, e.g. components of a digital telephone exchange, each include a pair of central processing units (CPUs) operating in master-slave relationship under the...
4648034 Busy signal interface between master and slave processors in a computer system  
A 32-bit central processing unit (CPU) having a six-stage pipeline architecture with an instruction and data cache memory and a memory management units, all provided on a single, integrated circuit...
4641238 Multiprocessor system employing dynamically programmable processing elements controlled by a master processor  
There is disclosed a multiple processor system which employs dynamically programmable processing elements (DDPE) utilized as slave devices and under the control of a master processor. A plurality...
4594654 Circuit for controlling external bipolar buffers from an MOS peripheral device  
A circuit for controls external bipolar buffers for an MOS peripheral device capable of operating in master end slave modes. The circuit provides for a slave mode logic block and a master mode...
4591967 Distributed drum emulating programmable controller system  
Master units and slave units are preferably housed in identical housings. Each master unit comprises a Central Intelligence Unit (CIU) which in turn comprises a drum processor and a communications...
4503513 Radio receiver system including a control unit and a remote unit  
An automobile radio receiver system includes a control unit located in the passenger compartment and a remote unit, for example, in the trunk compartment of the automobile. The control unit...
4497038 Electronic controller having a detachable front panel  
An electronic controller having a detachably mounted front panel unit on which display devices and control elements are arranged is disclosed. By means of the control elements, the process...
4495573 Method and device for transmission of digital data  
In a system comprising data-processing units, some of which are masters and others of which are slaves, all the units are connected to a common bus via interface circuits. Only the master units are...
4467412 Slave processor with clock controlled by internal ROM & master processor  
A graphical display of a video game is provided with "first person views" of game play, by generation of simulated three-dimensional perspectives. A slave computational unit relieves a master...
4396978 Multiprocessor system with switchable address space  
In a data processing system comprising at least two microcomputers, one microcomputer (1) serves as a master to control the or each other microcomputer (2, 3 respectively) as a slave. In order to...
4257099 Communication bus coupler  
A coupler pair provides the communication link between two multiprocessors wherein each multiprocessor comprises a plurality of master and slave devices interconnected by a communication bus. The...
4149238 Computer interface  
A computer interface for interconnecting a plurality of computer modules in a multiplex manner to emulate a computer configuration includes transmitters and receivers associated with each master...
4099236 Slave microprocessor for operation with a master microprocessor and a direct memory access controller  
An integrated circuit, slave microprocessor with its bus protocol is described. The slave unit may be activated by either a master microprocessor or a DMA controller. When activated by the DMA...
Matches 601 - 650 out of 654 < 1 2 3 4 5 6 7 8 9 10 11 12 13 14 >