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7594074 |
Storage system
To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data...
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7516313 |
Predicting contention in a processor
In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction,...
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7512813 |
Method for system level protection of field programmable logic devices
A method for protecting a dynamically reconfigurable computing system includes generating an encoding key and passing the encoding key, through a system level bus, to at least one field...
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7472212 |
Multi CPU system
A multi CPU system is capable of performing exclusive control of a plurality of CPUs accessing to the same resource by a hardware without depending on an OS. The plurality of CPUs are connected...
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7469308 |
Hierarchical bus structure and memory access protocol for multiprocessor systems
A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus...
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7389327 |
Control and monitoring system for power system
The object of the present invention is to make information necessary for judging whether control output is possible closer to the latest information than in the conventional method or made the...
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7350002 |
Round-robin bus protocol
A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During...
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7346720 |
Systems and methods for managing concurrent access requests to a shared resource
The systems and methods manage concurrent access requests to a shared resource. The systems and methods utilize an access management algorithm that permits multiple processes to concurrently obtain...
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7313794 |
Method and apparatus for synchronization of shared memory in a multiprocessor system
Method and apparatus for synchronizing access to a memory shared among a plurality of processors is described. In one example, each of the plurality of processors includes a primary bus for...
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7305510 |
Multiple master buses and slave buses transmitting simultaneously
A bus system, such as an internal bus system located within a digital device, is disclosed herein. The bus system comprises a plurality of master buses, each master bus connected to at least one...
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7209990 |
Maintain fairness of resource allocation in a multi-node environment
Locks are placed in a convert queue in a way that compensates for queue bias. Rather than always placing a remote lock in a queue at the tail, a remote lock can be placed further up in the queue,...
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7200765 |
Docking station for a wireless mouse with control of a computer
A docking station for a wireless mouse includes an output for communicating with a computer and a mouse detector for detecting when the mouse is docked in the docking station. The docking station...
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7197585 |
Method and apparatus for managing the execution of a broadcast instruction on a guest processor
A method and apparatus for managing the execution on guest processors of a broadcast instruction requiring a corresponding operation on other processors of a guest machine. Each of a plurality of...
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7162557 |
Competition arbitration system
A competition arbitration system in which chances for using a resource of a computer such as a bus or the like among devices are fair is provided. Pulses are sequentially generated periodically...
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7143223 |
Method, system and program product for emulating an interrupt architecture within a data processing system
To emulate an interrupt architecture in a data processing system, interrupt emulation code receives from an operating system a first call requesting access to a first resource in a first interrupt...
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7139854 |
Pipelining access to serialization tokens on a bus
Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed...
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7117282 |
Method and apparatus for active isolation of communications ports
A method and apparatus for isolating communications ports that allows access to a communications system for status and/or maintenance purposes via one communications port while preventing access to...
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7089339 |
Sharing of functions between an embedded controller and a host processor
An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables...
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7062583 |
Hardware semaphore intended for a multi-processor system
The invention relates to a method in a hardware semaphore lock (L 1 –LN) intended for a multi-processor system, which semaphore lock (L 1 –LN) protects a shared resource (R 1 –RN) in...
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7047336 |
Method for blocking request to bus
A method for blocking a request to a front side bus interconnected between a central processing unit (CPU) and a control chip includes the following steps. First, a bus ownership of the control...
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7032044 |
AV devices and method of controlling the same
In AV deices connected to a network via a digital interface, a connection request given from the outside via the network is rejected within a preset time after a connection state of the network...
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7024506 |
Hierarchically expandable fair arbiter
A plurality of arbitration devices is hierarchically coupled and has a plurality of child devices and at least one parent device. Each of the plurality of arbitration devices is operable to store a...
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7020725 |
Method of reserving isochronous resources in a network comprising a wireless link
A method for reserving an isochronous resource over a link between a first bus and a second bus, the link including a first interface device connected to the first bus and a second interface device...
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7013356 |
Methods and structure for preserving lock signals on multiple buses coupled to a multiported device
Structure and methods for preserving lock requests by master devices on multiple buses each coupled to a port of a multiported device. The invention provides for arbitration among multiple ports of...
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7007122 |
Method for pre-emptive arbitration
An interface system capable of providing pre-emptive arbitration among multiple agents comprises an interface including at least a first agent and a second agent which share the interface for...
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6973520 |
System and method for providing improved bus utilization via target directed completion
An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests...
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6963942 |
High availability system and method for improved intialization
To address the need for a high availability system ( 100 ) and method of initializing that address failures that lock up common communication buses ( 109 ) in these systems, the present invention...
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6944695 |
Method and apparatus for connecting devices to a bus
A two-wire serial (TWS) bus allows bus mastering by any device on the bus utilizing pull-ups. The bus is actively driven low, but typically pulled high by pull-up resistors for each device on the...
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6917996 |
Bus control system and method of controlling bus
An external bus control device 2 has first and second bus controllers 15, 16 and an external bus arbiter 17 . The bus controllers 15, 16 correspond to devices (for example, SRAM, DRAM)...
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6892261 |
Multiple operating system control method
An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one...
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6886064 |
Computer system serialization control method involving unlocking global lock of one partition, after completion of machine check analysis regardless of state of other partition locks
In a computer system having a logical-partitioned server, each partition of the server is provided with its own separate lock and access corridor, in addition to a global lock. When the locking of...
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6886063 |
Systems, devices, structures, and methods to share resources among entities
Systems, devices, structures, and methods are provided to allow resources to be shared among a plurality of processors. An exemplary system includes a mechanism to grant exclusive control of a...
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6865634 |
Method and apparatus for deadlock prevention in a distributed shared memory system
A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is...
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6832335 |
Transparent software emulation as an alternative to hardware bus lock
A method and apparatus for emulating hardware bus lock in a multi-architecture computer system includes a fault handler that acquires a semaphore reserved for bus lock and a semaphore that limits...
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6829698 |
Method, apparatus and system for acquiring a global promotion facility utilizing a data-less transaction
A data processing system includes a global promotion facility and a plurality of processors coupled by an interconnect. In response to execution of an acquisition instruction by a first processor...
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6782440 |
Resource locking and thread synchronization in a multiprocessor environment
Systems and methods are described for resource locking and thread synchronization in a multiprocessor environment. One method includes restricting access to a protected shared resource by use of a...
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6763469 |
Systems for local network security
Security systems for computers connected to networks transmitting packets are disclosed. One disclosed system includes a security agent and a local security device featuring a network hardware...
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6725308 |
Locking of computer resources
A computer processor includes a number of register pairs LOCKADD/LOCKCOUNT to hold values identifying when a computer resource is locked. The LOCKCOUNT register is incremented or decremented in...
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6725306 |
DEBUG mode for a data bus
A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a...
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6715049 |
Microcomputer and information processing system
A microcomputer and an information processing system protect data stored therein and secure the safety of the data. The microcomputer ( 1 ) has a memory ( 3 ), a read protect register ( 13 ), and a...
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6697899 |
Bus control device allowing resources to be occupied for exclusive access
If an uncachable write from a processor 300 is held in a processor request buffer 130 when a request control circuit 180 detects that a transaction for a cachable read to the processor 300 ...
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6651124 |
Method and apparatus for preventing deadlock in a distributed shared memory system
A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is...
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6631419 |
Method and apparatus for high-speed longest prefix and masked prefix table search
According to one embodiment ( 100 ) a system may receive a multi-bit input value (DEST_IP) and split it into a number of portions (L 1 bits, L 2 bits and L 3 bits). A first portion (L 1 bits) can...
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6622184 |
Information processing system
An information processing system which makes it possible to protect information stored in the ROM of the system from unauthorized access by means of a debug tool. The information processing system...
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6598104 |
Smart retry system that reduces wasted bus transactions associated with master retries
The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart...
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6577905 |
Apparatus and method for providing a transient port
An apparatus and method for providing a transient connection port are provided. Further, an apparatus and method for switching between a permanent connection port and a transient connection port...
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6574755 |
Method and processing fault on SCSI bus
A method for processing a SCSI bus fault in a SCSI system which has an initiator device and a target device interconnected via a SCSI bus. In response to a control command, the initiator device...
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6546508 |
Method and apparatus for fault detection of a processing tool in an advanced process control (APC) framework
A method and apparatus for providing fault detection in an Advanced Process Control (APC) framework. A first interface receives operational state data of a processing tool related to the...
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6546443 |
Concurrency-safe reader-writer lock with time out support
Synchronization services provide a concurrency-safe reader/writer lock supporting a time out feature. The lock can be implemented using lockless data structures to provide efficient synchronization...
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6532507 |
Digital signal processor and method for prioritized access by multiple core processors to shared device
A system and signal processing method, in which at least two processors have prioritized, shared access to one or more devices connected along a bus. In preferred embodiments, a fast processor is...
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