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7613928 |
Flash device security method utilizing a check register
A security method for preventing accidental or unauthorized writes to a flash memory. According to one embodiment of the present invention, a BIOS program stored in a flash memory array generates a...
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7610421 |
Bus request control circuit
A bus request control circuit provided in a signal processing circuit having a higher priority in an arbitration circuit includes a request signal transmitting section which transmits a request...
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7609713 |
Associating a signal measurement with a communication device on a network
A signal measured on a network is associated with one of a plurality of communication devices connected to the network. The designation address of an active communication device that is scheduled...
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7609540 |
Serial bus controller using nonvolatile ferroelectric memory
A serial bus controller using a nonvolatile ferroelectric memory is provided. The memory controller structure using a nonvolatile ferroelectric register enables control of variable access time...
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7603478 |
Displaying routing information for a measurement system
Computer-implemented system and method for presenting routing information in a measurement system. A meta-routing tool receives user input specifying a device, then retrieves a topography...
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7598948 |
System and method of detecting rotated displays
A system for adjusting display data orientation. The system includes graphics circuitry to send and receive control signals over a set of control lines. The exchange of control signals is governed...
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7594074 |
Storage system
To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data...
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7594042 |
Effective caching mechanism with comparator coupled to programmable registers to store plurality of thresholds in order to determine when to throttle memory requests
A system includes a plurality of bus masters that generate direct memory access requests to access a protected memory device. Before granting the access, the system checks for memory protection...
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RE40921 |
Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it...
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7590140 |
Method for addressing the participants of a bus system
In the method for addressing the participants of a bus system, the central control unit connects the bus line to one potential of the operating voltage, while each participant tries to pull the bus...
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7587523 |
Distributed systems for determining card status
The master/slave arbitration process includes a voting process that allows cards within the system to use voting to determine the health of each of the individual cards. The voting process thereby...
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7580811 |
Medical data communication interface monitoring system
A system maintains statistics on DICOM interfaces that include for each interfaced Application Entity, the number, timing and types of DICOM failures, number and timing of broken network...
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7565467 |
USB hub, USB-compliant apparatus, and communication system
A USB hub according to an embodiment of the invention includes: a USB upstream port unit for inputting/outputting data in accordance with a USB protocol; a wireless upstream port unit for...
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7565420 |
Method for initializing a distributed software architecture and an electronic system
The present invention relates to a method for initializing a distributed software architecture as well as an electronic system. A control module for a network function is made available in the form...
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7562143 |
Managing escalating resource needs within a grid environment
A job is submitted into a first selection of resources in a grid environment from among a hierarchy of discrete sets of resources accessible in the grid environment. Discrete sets of resources may...
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7558944 |
Microcomputer
A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6 , and made accessible in parallel by third buses XAB and XDB and second buses...
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7552289 |
Method and apparatus for arbitrating access of a serial ATA storage device by multiple hosts with separate host adapters
An adapter unit operative to support access of an SATA storage device by a plurality of hosts associated with separate host adapters. The adapter unit includes a multiplexer coupled to an arbiter....
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7552257 |
Data transmission device with a data transmission channel for the transmission of data between data processing devices
The present invention provides a data processing apparatus having at least one dedicated data processing device ( 10 ) of a first type, a central data processing device ( 4 ) for controlling...
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7549009 |
High-speed PCI interface system and a reset method thereof
A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at...
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7543094 |
Target readiness protocol for contiguous write
A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle,...
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7529861 |
Peripheral switching device and a peripheral switching control device
A peripheral switching device includes an ownership switch request receiver unit configured to receive an ownership switch request for requesting to assign a peripheral to an operating system; an...
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7529268 |
Multi-point electronic control system protocol
A generic software protocol allows communication between multiple devices within an electronic control system as well as between an electronic control system and an external monitoring device. The...
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7523268 |
Reducing number of rejected snoop requests by extending time to respond to snoop request
A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if...
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7519774 |
Data processor having a memory control unit with cache memory
The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external...
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7519752 |
Apparatus for using information and a count in reissuing commands requiring access to a bus and methods of using the same
In a first aspect, a first method of reissuing a command involving bus access is provided. The first method includes the steps of (1) storing information associated with commands that are to be...
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7519751 |
Method of generating an enable signal of a standard memory core and relative memory device
A memory device is configured for communicating with one of two different serial protocols, respectively an LPC or an SPI protocol, as well as with a parallel communication protocol through a...
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7516313 |
Predicting contention in a processor
In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction,...
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7512729 |
Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency
A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes...
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7509446 |
IIC bus communication system capable of suppressing freeze of IIC bus communication due to a noise and method for controlling IIC bus communication
Multiple master devices and multiple slave devices are connected in parallel to two bus lines including a SCL line 1 and a SDA line 2 , and a pullup resistor is connected between the bus lines...
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7508981 |
Dual layer bus architecture for system-on-a-chip
A dual layer bus architecture for a system-on-a-chip (SOC) is disclosed. The bus architecture comprises a main bus adapted to connect a microprocessor, an image capture module, and a dual master...
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7506085 |
System and method for sending data across a bus cable having in-band and side-band signal conductors
A method and apparatus for sending data. One exemplary embodiment may be a method comprising sending a data rate synchronization pulse from drive controller in a computer system to a storage device...
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7500042 |
Access control device for bus bridge circuit and method for controlling the same
An access control device having a number-of-waits setting circuit determining a wait periodicity corresponding to an operating speed of peripheral devices connected to a second bus according to an...
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7493425 |
Method, system and program product for differentiating between virtual hosts on bus transactions and associating allowable memory access for an input/output adapter that supports virtualization
A method, system and computer program product that allows a System Image within a multiple System Image Virtual Server to maintain isolation from the other system images while directly exposing a...
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7487281 |
Computer system to control the data transfer between a memory and a peripheral device connected to a CPU via a bus
In a computer system that includes a memory, a peripheral device to which an address overlapping with a part of an address space assigned to the memory is assigned, a CPU for sending a signal...
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7486637 |
Wireless communication method and system for efficiently managing paging windows and data messages
A wireless communication method and system for efficiently managing paging windows and data messages. The wireless communication system includes at last one network and a plurality of user...
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7484046 |
Reducing number of rejected snoop requests by extending time to respond to snoop request
A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address,...
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7483422 |
Data processing system, method and interconnect fabric for selective link information allocation in a data processing system
A data processing system includes a plurality of processing units coupled for communication by a communication link and a configuration register. The configuration register has a plurality of...
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7475176 |
High bandwidth split bus
A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing...
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7467245 |
PCI arbiter
A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data...
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7467179 |
Backplane architecture for a data server
A media server for use in networks where media are transmitted in packet form comprises at least one card shelf containing at least one bus controller card, at least one other card such as a media...
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7464207 |
Device operating according to a communication protocol
A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a...
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7461190 |
Non-blocking address switch with shallow per agent queues
In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage...
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7460061 |
Distributed radar data processing system
A distributed radar data processing system for generating data to be supplied to air traffic control by processing radar data obtained from a radar device, comprises a plurality of data buses...
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7457901 |
Microprocessor apparatus and method for enabling variable width data transfers
A microprocessor including processor logic and sparse write logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction,...
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7457886 |
System and method for input/output scheduling
A system and method for Input/Output scheduling are described herein. In one embodiment, the method includes installing a plurality of Input/Output (I/O) schedulers to schedule I/O requests for a...
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7454576 |
System and method for cache coherency in a cache with different cache location lengths
A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups...
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7441059 |
Method and device for data communication
A device for data communication between a first host device or a further host device and at least one client device along a shared transmission path includes a first host device, which includes a...
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7429990 |
Network management card for use in a system for screen image capturing
A network management card is provided to capture a screen image of a host system for transmission over a computer network for remote viewing and remote system management. The network management...
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7428607 |
Apparatus and method for arbitrating heterogeneous agents in on-chip busses
A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and...
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7426601 |
Segmented interconnect for connecting multiple agents in a system
In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises...
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