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7114038 Method and apparatus for communicating between integrated circuits in a low power mode  
For one embodiment, a computer system includes both high power and low power buses coupling a processor to a controller. When the processor is in a high power mode, its cache is snooped by the...
7107374 Method for bus mastering for devices resident in configurable system logic  
A processor is connected to a configurable system interconnect (CSI) bus. A CSL is connected to the CSI bus. The CSL comprises a first set of signal lines to send a data transfer request and a...
7107375 Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology  
An arbitration elimination scheme for a bus. In a preferred embodiment, a programmable counter determines when a SCSI bus idle condition is reached and when a portion of an arbitration window for...
7103689 Method for automatic replacement in automation technology field devices where swapping is not necessary  
A method for operating an automation technology field device connected via a bus system with a superordinated unit and having an identifier identifying the type of the field device, at least one...
7103696 Circuit and method for hiding peer devices in a computer bus  
Circuit and method for hiding peer devices from a computer host are provided. The devices and host share a common electrical bus, e.g., a PCI bus. The method allows to generate a signal indicative...
7100160 Method and system for implementing host-dependent SCSI behavior in a heterogeneous host environment  
A method, system, and program product is provided for configuring a target device, the method comprising the steps of: receiving a log-in request to connect the target device to a host, wherein...
7099968 System and method for generating bus requests in advance based on speculation states  
A system and method predict when to generate a bus request ahead-of-time based on bus-activity, bus-usage efficiency and bus-bandwidth usage. A bus-usage efficiency indicator may be generated by a...
7096307 Shared write buffer in a peripheral interface and method of operating  
A data processing system has a single configurable write buffer within a peripheral interface unit that is shared among multiple peripherals. Configuration registers are dynamically programmed to...
7096289 Sender to receiver request retry method and apparatus  
Disclosed is a method for and an apparatus using various factors including system performance feedback data to optimize the time suggested to attempt retry of a request. Among the factors used...
7096293 Dynamic bus arbitration method and bus arbiter  
A method of arbitrating a system bus shared by a CPU, which is a first master device, and second and third master devices comprises storing a first bus occupancy rate for each master device and a...
7093041 Dual purpose PCI-X DDR configurable terminator/driver  
A dual purpose PCI-X DDR configurable terminator/driver providing programmable termination of the interface in a PCI-X system a plurality of N-channel devices divided into at least two groups and...
7093044 Method and apparatus for providing quality-of-service delivery facilities over a bus  
The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an...
7093053 Console chip and single memory bus system  
A single memory bus multi-media computer system is provided, including a CPU/Sound/Graphic unit, a bus arbitrator, a program and sound and graphic memory for communicating with the...
7093152 Semiconductor device with a hardware mechanism for proper clock control  
A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which...
7089340 Hardware management of java threads utilizing a thread processor to manage a plurality of active threads with synchronization primitives  
A system for managing threads to handle transaction requests connected to input/output (I/O) subsystems to enable notification to threads to complete operations.
7089339 Sharing of functions between an embedded controller and a host processor  
An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables...
7085863 I2C device including bus switches and programmable address  
An I2C device is disclosed that includes a main I2C section, bus switches, switch logic, and address logic as part of the I2C device. The I2C device is coupled to an I2C bus for communicating with...
7085865 I/O throughput by pre-termination arbitration  
The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention...
7085864 Method and structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter  
An overrun data handling circuit in a SCSI initiator and an overrun data handling method automatically handle Packetized SCSI Protocol data overruns. A multi-data channel host adapter includes the...
7082485 Systems and methods for establishing peer-to-peer communications between network devices communicating via a common bus  
A system for establishing peer-to-peer communications via a network bus comprises a bus controller and at least one peer-to-peer grouping including a source device and at least one receiving...
7080174 System and method for managing input/output requests using a fairness throttle  
A system and method for providing a desired degree of fairness of access to data transfer resources by a plurality of command-initiating bus agents. A bus arbiter allocates general ownership of...
7076574 Method and system for disconnecting a specific channel of a SCSI controller  
A method for disconnecting a channel of a SCSI (small computer system interface) controller from a SCSI bus is disclosed. The method includes receiving a signal that prompts the SCSI controller to...
7076587 Buffer management in packet switched fabric devices  
A buffer management system for cooperating with a packet based switching system is proposed. The purpose of this system is to reduce traffic congestion, ameliorate its effects, provide fairness to...
7076585 System bus controller and the method thereof  
A system bus controller for a computer system and a related method are introduced. The computer system has at least a bus and a bus master electrically connected to the bus. The system bus...
7076593 Interface bus optimization for overlapping write data  
Embodiments of the present invention are devices with a queue for receiving a plurality of data write requests and having a means for comparing the data write requests in the queue and then...
7075546 Intelligent wait methodology  
A central processing unit (CPU) configured to apply an intelligent wait methodology is provided. The CPU includes a chip select module that defines a chip select signal associated with an external...
7076583 Multiprocessor system, shared-memory controlling method, recording medium and data signal embedded in a carrier wave  
A multiprocessor system includes a plurality of processors, a shared memory shared by the plurality of processors and a contention determiner which manages access to the shared memory by each of...
7076582 Bus precharge during a phase of a clock signal to eliminate idle clock cycle  
A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an...
7073001 Fault-tolerant digital communications channel having synchronized unidirectional links  
A method of synchronizing or initiating channel lock in a serial loop formed by an initializing transceiver and subject transceivers disclosed. Should a transceiver in the serial loop detect that...
7069362 Topology for shared memory computer system  
A dual ring topology for multiprocessing computer systems. The dual ring topology interconnects multiple building blocks (nodes) to each other, each node comprising processing elements, memory and...
7069361 System and method of maintaining coherency in a distributed communication system  
A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into...
7065594 Method and apparatus of allocating minimum and maximum bandwidths on a bus-based communication system  
Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the...
7058741 System for suspending processing by a first electronic device on a data line to allow a second electronic device to use the data line, with subsequent resumption of the processing of the first electronic device  
To provide a method for controlling a transmission system with quick response in which plural electronic devices are connected to one host apparatus through a common data line. The method for...
7058179 Method and system for a secure high bandwidth bus in a transceiver device  
A transceiver system for receiving content contained in a secure digital broadcast signal. The transceiver system includes a first component for generating a data stream from a received digital...
7054771 Bus line current calibration  
Disclosed herein is a method and system for calibrating line drive currents in systems that generate data signals by varying line drive currents and that interpret the data signals by comparing...
7054966 Data processing system  
A data processing system in accordance with an exemplary embodiment is provided. The data processing system includes a first host device operably coupled to a first PCI communication bus wherein...
7054969 Apparatus for use in a computer system  
Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module...
7051131 Method and apparatus for recording and monitoring bus activity in a multi-processor environment  
A method and apparatus to facilitate a history trace of system bus activity in a Symmetric Multi-Processor (SMP) environment. A dynamic scan capability is provided to User (516) via Computer (504)...
7051132 Bus system and path decision method therefor  
A bus system and a method of deciding a data transmission path are provided. The bus system includes a plurality of functional blocks; a ring bus which transmits data in a single direction; an...
7043568 Configuration selection for USB device controller  
A selection system for configuring a device controller. The selection system includes a plurality of state machines each of which has a portion of the configuration information needed to inform a...
7043579 Ring-topology based multiprocessor data access bus  
The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a...
7039749 Method and apparatus for switching on a VXS payload module  
A multi-service platform system (200) having a VXS backplane (204) includes a VXS payload module (202) coupled to the VXS backplane, a first switched fabric enabled mezzanine card (212) coupled to...
7039047 Virtual wire signaling  
A method and apparatus for implementing virtual wire signaling is described. It includes an apparatus including a first component, a bus coupled to the first component, the bus to transmit packets...
7035981 Asynchronous input/output cache having reduced latency  
The present invention is generally directed to a device including an asynchronous input/output (I/O) data cache. The device includes a single data storage area that is disposed in communication...
7028117 Structure for handling packetized SCSI protocol data overruns in a multi-data channel host adapter  
An overrun data handling circuit in a SCSI initiator automatically handles Packetized SCSI Protocol data overruns. A multi-data channel host adapter includes the overrun data handling circuit that...
7028115 Source triggered transaction blocking  
A system may include at least a first agent and a second agent, and the first agent may be coupled to receive a block signal generated by the second agent. The block signal is indicative of...
7020191 Network device and method for detecting a link failure which would cause network to remain in a persistent state  
A network device monitors a signal transmitted to a wireless or optical link and a signal received from the link for detecting a bit-by-bit coincidence between them. In response to the detection...
7020733 Data bus system and method for performing cross-access between buses  
A data bus system, capable of distributing devices including first and second data buses capable of transmitting data among a plurality of devices; a register block that stores information on a...
7007110 Nak throttling for USB host controllers  
A method and apparatus for traversing a schedule with a bus master, the schedule having a plurality of elements, each element having information pertaining to one of a plurality of endpoints;...
7003606 Electronic device, method for using electronic device, and electronic device system for reserving bus usage time on a bus to conduct communications between electronic devices  
An IRD 103 supplies broadcasting data on a bus in a desired time period. When the IRD 103 performs a reservation of the bus usage, the IRD 103 requests current bus usage information and...