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7284078 Deterministic field bus and process for managing same such that when transmissions from one subscriber station are enabled transmissions from other subscriber stations are disabled  
This invention relates to a deterministic field bus and a process for management of this bus enabling communication of messages between several subscriber stations each comprising at least one...
7284083 Dynamically configuring resources for cycle translation in a computer system  
A method and system that enables customized computer machines to be more readily developed by removing the function of resource translation out of the hardware abstraction layer (HAL). A machine...
7272151 Centralized switching fabric scheduler supporting simultaneous updates  
A system for servicing data transactions within a processing device using common data paths. The system is broadly comprised of: a plurality of source agents operable to transmit a plurality of...
7269675 Method and device for monitoring a bus system and bus system  
A method and device for monitoring a bus system and bus system having at least two users, of which at least one is structured as an authorized user and monitors the data transmission on the bus...
7266626 Method and apparatus for connecting an additional processor to a bus with symmetric arbitration  
A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An...
7266024 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Memory systems with variable delays for write data signals
 
Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a...
7260662 I2C bus controlling method  
A module has an IC for communication control (a PHY unit) and an EEPROM (or MCU) connected to the PHY unit via an I2C bus. When a software reset is triggered while the PHY unit reads non-volatile...
7254688 Data processing apparatus that shares a single semiconductor memory circuit among multiple data processing units  
Multiple data processing circuits may share a semiconductor memory circuit, such as double-data-rate synchronous dynamic random access memory (DDR-SDRAM). A data processing circuit (202-1 or...
7254115 Split-transaction bus intelligent logic analysis tool  
An improved split-transaction bus intelligent logic analysis tool has a bus synchronizer, a decoder and a logic analysis function. The bus synchronizer is configured to receive link traffic and...
RE39763 Isochronous channel having a linked list of buffers  
A computer system consists of a plurality of nodes, each with an associated local host, coupled together with a plurality of point-to-point links. An isochronous data channel is established within...
7251702 Network controller and method of controlling transmitting and receiving buffers of the same  
In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from...
7246185 Master and slave side arbitrators associated with programmable chip system components  
Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system....
7246184 Method for configuring and/or operating an automation device  
A method and an engineering system, which reduce the extent of configuration work with regard to a possible expansion of the automation device. A configured automation device can thus be expanded...
7240134 Circuit with processing prevention unit  
Circuit having a bus, a first receiver circuit part coupled to the bus for processing a signal on the bus, a second receiver circuit part coupled to the bus for processing a signal on the bus, a...
7240140 Efficient detection of multiple assertions in a bus  
A mechanism detects multiple assertions in a bus efficiently by encoding each of N bus lines with log2(N) pairs of bit lines.
7237054 Switching interfaces in external disk drives  
In an external disk drive system comprising a disk drive, a bridge controller comprising a plurality of Bridge Controller Host (BCH) interfaces adapted to establish communication between the...
7231473 Dual channel universal serial bus structure  
A Dual Channel Universal Serial Bus (DCUSB) structure compatible with USB 1.0, USB 1.1 or USB 2.0 protocols for higher data transmission rate comprising of two data transmission channels each with...
7228263 Method for representing root busses using object oriented abstractions  
A method for representing root busses and their subordinate bus configurations using an object oriented abstraction scheme that enables various system components to communication with peripheral...
7218638 Switch operation scheduling mechanism with concurrent connection and queue scheduling  
A system for servicing data transactions within a processing device using common data paths. The system is broadly comprised of: a plurality of source agents operable to transmit a plurality of...
7206877 Fault tolerant data communication network  
The present invention provides a fault tolerant bus architecture and protocol for use in an Integrated Hazard Avoidance System of the type generally used in avionics applications. In addition, the...
7203788 USB-to-VGA converter  
A USB-to-VGA converter includes a USB controller connectable to a USB port of a computer for receiving USB based display signals from the computer, a VGA controller connectable to a display device...
7203779 Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus  
A bus arbitrator for use in a shared bus system in which N bus devices request access to a shared bus. The bus arbitrator slowly activates and rapidly de-activates tristate line drivers coupled to...
7203773 Multi-protocol A/V control port with selective modulation  
A method and apparatus for using a control port in accordance with a variety of different protocols. A main processor communicates a configuration instruction to an interface controller. The...
7200575 Managing access to digital content  
Systems and methods of managing access to digital content are described. In one aspect, a novel digital content access management system enables users to register previously owned digital content...
7200781 Detecting and diagnosing a malfunctioning host coupled to a communications bus  
Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.
7197577 Autonomic input/output scheduler selector  
The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped...
7185120 Apparatus for period promotion avoidance for hubs  
A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction...
7181558 Avoidance of extended bus occupancy through simple control operation  
A shared bus system includes a bus, a first circuit which accesses the bus, a second circuit which shares the bus with the first circuit, and accesses the bus, a counter circuit which is provided...
7177966 Microcomputer minimizing influence of bus contention  
An edge detecting circuit detects an input level change (edge) of a synchronous signal provided from a synchronous signal input terminal. A data latch unit latches digital data provided from an...
7177965 Linking addressable shadow port and protocol for serial bus networks  
Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or...
7174412 Method and device for adjusting lane ordering of peripheral component interconnect express  
A method for adjusting the PCI Express lane ordering is disclosed, comprising the following steps. The first packet associated with a first PCI Express lane ordering is sent to the peripheral...
7174403 Plural bus arbitrations per cycle via higher-frequency arbiter  
An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or...
7174402 Systems, network devices and methods for highly configurable peer-to-peer communications between network devices communicating via a common bus  
A system and method are provided for initiating peer-to-peer communications via a network bus. The system includes a bus controller in electrical communication with the network bus for controlling...
7173877 Memory system with two clock lines and a memory device  
The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory...
7167928 Electronic device with USB interface  
A mobile device 1 has a USB transmitter-receiver 3 having one or more interfaces formed by one or more endpoints for exchanging information via the USB, one or more logical devices 61 to 65...
7162557 Competition arbitration system  
A competition arbitration system in which chances for using a resource of a computer such as a bus or the like among devices are fair is provided. Pulses are sequentially generated periodically...
7162591 Processor memory having a dedicated port  
Methods and apparatus are provided for closely coupling a dedicated memory port to a processor core while allowing external components access to the dedicated memory. A processor core such as a...
7155555 Communication system and method of controlling same  
Cancellation of transmission of print data from a host computer to a printer is implemented under a USB Printer Class protocol without increasing the burden upon a printer on the receiving side....
7155553 PCI express to PCI translation bridge  
A PCI Express to PCI bridge enables upstream and downstream isochronous data transfer by modifying the PCI bus arbiter so that the PCI device on the PCI bus is treated as a virtual port for the...
7143220 Apparatus and method for granting concurrent ownership to support heterogeneous agents in on-chip busses having different grant-to-valid latencies  
A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and...
7143217 Device configuration  
In one embodiment, a method is provided. The method of this embodiment may include receiving an indication that a first device has been granted access to a bus. In response, at least in part, to...
7143227 Broadcast bridge apparatus for transferring data to redundant memory subsystems in a storage controller  
A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write...
7139854 Pipelining access to serialization tokens on a bus  
Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed...
7130947 Method of arbitration which allows requestors from multiple frequency domains  
The present invention provides a method of arbitration for resources which allows requestors from multiple frequency domains. Most requestors generate requests at full speed. A small number of...
7127544 Data transfer apparatus and data transfer method  
A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. Data...
7124223 Routability for memory devices  
A computer system provides improved routability for memory modules. Chips are placed on the back side of the module directly behind the chips on the front side, and vias connects destination pins...
7124410 Distributed allocation of system hardware resources for multiprocessor systems  
A method is provided for allocating system resources across multiple nodes of a system communicating through a hardware device. The method provides for allocation of transaction units or...
7120706 Contention resolution in a memory management system  
A memory management system for resolving contention for access to a plurality of memories. Signals are continuously applied to an access flow regulator indicating the busy/idle state of each...
7117281 Circuit, system, and method for data transfer control for enhancing data bus utilization  
In a system having a plurality of bus masters, system and method for enhancing data bus utilization are disclosed. This system comprises: a data bus connected to a peripheral apparatus and...
7117282 Method and apparatus for active isolation of communications ports  
A method and apparatus for isolating communications ports that allows access to a communications system for status and/or maintenance purposes via one communications port while preventing access...