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7483422 Data processing system, method and interconnect fabric for selective link information allocation in a data processing system  
A data processing system includes a plurality of processing units coupled for communication by a communication link and a configuration register. The configuration register has a plurality of...
7484046 Reducing number of rejected snoop requests by extending time to respond to snoop request  
A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of...
7475176 High bandwidth split bus  
A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing...
7467245 PCI arbiter  
A bus arbiter that ensures high priority transfers complete and allows high-priority data transfers with specific latency requirements, such as 802.11 requirements, to be prioritized above data...
7467179 Backplane architecture for a data server  
A media server for use in networks where media are transmitted in packet form comprises at least one card shelf containing at least one bus controller card, at least one other card such as a media...
7464207 Device operating according to a communication protocol  
A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, as a...
7460061 Distributed radar data processing system  
A distributed radar data processing system for generating data to be supplied to air traffic control by processing radar data obtained from a radar device, comprises a plurality of data buses...
7461190 Non-blocking address switch with shallow per agent queues  
In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage...
7457886 System and method for input/output scheduling  
A system and method for Input/Output scheduling are described herein. In one embodiment, the method includes installing a plurality of Input/Output (I/O) schedulers to schedule I/O requests for a...
7457901 Microprocessor apparatus and method for enabling variable width data transfers  
A microprocessor including processor logic and sparse write logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction,...
7454576 System and method for cache coherency in a cache with different cache location lengths  
A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include...
7441059 Method and device for data communication  
A device for data communication between a first host device or a further host device and at least one client device along a shared transmission path includes a first host device, which includes a...
7429990 Network management card for use in a system for screen image capturing  
A network management card is provided to capture a screen image of a host system for transmission over a computer network for remote viewing and remote system management. The network management...
7428607 Apparatus and method for arbitrating heterogeneous agents in on-chip busses  
A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and...
7426601 Segmented interconnect for connecting multiple agents in a system  
In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect...
7421520 High-speed I/O controller having separate control and data paths  
An I/O controller having separate command and data paths, thereby eliminating the bandwidth used by the commands and thus increasing bandwidth available to the data buses. Additionally, the I/O...
7414875 Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules  
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being...
7412579 Secure memory controller  
A memory controller partitions memory into secure partitions and non-secure partitions.
7409482 Computer and method for on-demand network access control  
A computer and method that control access to a network. The computer includes an application that shrinks the window of opportunity for a network attack and reduces power consumption by...
7406557 Programmable logic device including programmable interface core and central processing unit  
A programmable logic device (PLD) includes a central processing unit (CPU) and a programmable interface coupled to the CPU, wherein the programmable interface includes a core designated by a user....
7406552 Systems and methods for early fixed latency subtractive decoding including speculative acknowledging  
Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively, or conditionally, acknowledges a bus transaction within a fixed time...
7404024 Method for arbitrating access to a shared resource  
A method for arbitrating access to a resource shared by several electronic elements. Each element is allocated a first counting value and a first penalty, the first counting value is decremented...
7404019 Method and apparatus for endianness control in a data processing system  
A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the...
7401126 Transaction switch and network interface adapter incorporating same  
A transaction switch and integrated circuit incorporating said for switching data through a shared memory between a plurality of data interfaces that support different data protocols, namely...
7398336 Switching device for RS-232 serial port and USB serial port  
A switching device for RS-232 serial port and USB serial port is adapted to simultaneously provide a RS-232 serial port and a USB serial port for a micro-processor with a single USART. The...
RE40389 Generating a serial number from random numbers  
A process for generating a serial number from a random number is suitable for being used on a device that uses serial number in a bus. First, this process generates a serial number for use from a...
7383363 Method and apparatus for interval DMA transfer access  
A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from...
7369550 Method and apparatus for locking a table in a network switch  
An apparatus and method are disclosed for locking a table within a network switch. The table is used to store entries that contain addresses of network stations connected to the network switch. A...
RE40261 Apparatus and method of partially transferring data through bus and bus master control device  
A method of transferring data through a bus includes the steps of: occupying the bus by a first device serving as a bus master; transferring a first predetermined number of data items of all data...
7346719 Systems, methods, and bus controllers for creating an event trigger on a network bus  
The present invention provides systems, methods, and bus controllers (12) for monitoring an event of interest via a network bus (14) and creating an asynchronous event trigger on the network bus...
7346722 Apparatus for use in a computer systems  
Apparatus for use in a computer system comprises a bus architecture, a plurality of modules connected to the bus architecture, at least one module being latency tolerant and at least one module...
7343436 Synchronous electronic control system and system control method  
The present invention is carried out to provide a system controller, a control system and a system control method which are inexpensive, highly stable, capable of storing all information and past...
7340542 Data processing system with bus access retraction  
A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access...
7340171 FTTH system for broadcast/communication convergence using IEEE 1394  
A broadcast/communication convergence system, and an FTTH (Fiber To The Home) system that can accommodate broadcast signals of various channels and variable band signals by converging broadcast...
7337258 Dynamically allocating devices to buses  
Devices are assigned to different buses at development time as well as dynamically during operation, based on actual performance. At development time, bus assignment can be determined based on...
7330924 Network media access controller embedded in a programmable logic device—physical layer interface  
An aspect of the invention is physical layer interface for a network interface including a plurality of input/output pins. The input/output pins are coupled for being multiplexed into a physical...
7328289 Communication between processors  
A method of communicating between a first and a second processor includes the first processor sending a datum over a common control bus, and the second processor receiving the datum from the...
7328291 System and method for controlling the service engagement in a data bus system  
Data bus system and method are provided for controlling service engagements for bus users. At least one bus user provides services and other bus users use these services. A resource manager stores...
RE40034 Method and apparatus to reduce serial communications path connection overhead  
Control of a loop of a fiber-channel arbitrated-loop serial communications channel is maintained (i.e., the loop connection is held open) as long as a minimum amount of data, which optionally is...
7320040 Data distribution system  
A transfer apparatus receives, from a controller, a bit string including a plurality of individual data addressed to plural input/output units. The bit string is divided into data fragments. The...
7310694 Reducing information reception delays  
A technique for reducing information reception delays is provided. The technique reduces delays that may be caused by protocols that guarantee order and delivery, such as TCP/IP. The technique...
7301657 Printer including video decoder  
A printer includes an interface for receiving compressed digital video; and a circuit for performing video-decoding of the compressed video received by the interface. Such a printer can print...
7302508 Apparatus and method for high speed data transfer  
An improved target and initiator. The initiator provides a starting address and length information on a bus synchronously with a clock signal. While the starting address and length information are...
7301831 Memory systems with variable delays for write data signals  
Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a...
7293125 Dynamic reconfiguration of PCI express links  
A method and circuitry for dynamically reconfiguring the links of a PCI Express bus. A computer system has been initially configured with PCI Express bus links to various endpoints, using the...
7293129 Flexible routing and addressing  
At an ingress point to a shared transaction infrastructure, for example a shared PCI Express infrastructure, an entry in a segment table maps an address in a transaction packet to a target for the...
7290065 Method, system and product for serializing hardware reset requests in a software communication request queue  
A system, method, and product are disclosed in a data processing system for serializing hardware reset requests in a software communication request queue in a processor card. The processor card...
7287109 Method of controlling a memory device having a memory core  
Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the...
7285975 Termination providing apparatus mounted on memory module or socket and memory system using the apparatus  
Provided are an apparatus which provides termination with respect to signals transmitted through a bus line, and a memory system using the apparatus which can prevent the number of sockets from...
7287110 Storage device for a multibus architecture  
A storage device for a multibus architecture includes at least one memory to store data, information, and/or addresses, along with a memory connection having a port to connect the memory to one of...