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7689991 Bus management techniques  
Techniques to prevent interruption of operations performed by an I/O device. One advantage may be that the I/O device does not need to re-establish its interrupted operation (and waste the...
7688838 Efficient handling of work requests in a network interface device  
A method for communication includes inputting from a host processor to a network interface device a sequence of work requests indicative of operations to be carried out by the network interface...
7685344 Method of setting priority of devices connected to bus, and apparatus having a plurality of devices and arbiter  
The remaining time period until the deadline of transfer by a device connected to a bus is measured, the remaining data size to be transferred by the device is detected, and the priority level of...
7676621 Communications bus transceiver  
A computer system is disclosed that includes: a communications bus implemented in accordance with an Inter-IC bus specification; a bus controller coupled to the communications bus; a send machine...
7673104 Information processing apparatus, system controller, local snoop control method, and local snoop control program recorded computer-readable recording medium  
The present invention relates to an information processing apparatus equipped with a plurality of storage units and a plurality of system controllers sharing communication control on the plurality...
7664896 Expedited completion done messages, method and apparatus  
A method to provide more opportunities to close a connection in an orderly fashion and avoid abrupt break of the connection. A device and a system operable to practice such as method.
7660925 Balancing PCI-express bandwidth  
Mechanisms for balancing bus bandwidth across a plurality of PCI-Express (PCIe) endpoints are provided. Firmware automatically operates in concert with established data structures to set...
7660924 Semiconductor integrated circuit device which executes data transfer between a plurality of devices connected over network, and data transfer method  
A semiconductor integrated circuit device includes a first semiconductor device and a second semiconductor device, first and second buffer circuits, a data bus, and a control circuit. The...
7647441 Communications system and method with multilevel connection identification  
An embodiment includes a communication medium coupled to a plurality of the functional blocks in an integrated circuit. Three or more of the initiator functional blocks communicate with a target...
7647515 System and method for information handling system adaptive variable bus idle timer  
Power management of an information handling system PCI Express bus dynamically adjusts the inactivity time at the bus that is determined before initiation of a low power state by analyzing the...
7644219 System and method for managing the sharing of PCI devices across multiple host operating systems  
A system and method is disclosed for initializing PCI devices in a computer system or information handling system. Upon initialization of the system, each operating system instance of the system...
7640446 System-on-chip power reduction through dynamic clock frequency  
A dynamic clock frequency module for a system-on-chip (SOC) including modules that communicate over a system bus includes a request evaluation module that receives requests to utilize the system...
7634603 System and apparatus for early fixed latency subtractive decoding  
Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the...
7631348 Secure authentication using a low pin count based smart card reader  
A computer system may receive one or more credentials of a user (e.g., username, password, etc.) from an integrated circuit (IC) device carried by the user. The computer system may include an IC...
7631129 Computer monitoring system and monitoring method  
An exemplary computer monitoring system includes a central processing unit (CPU) connected to a computer, a first microprocessor, a second microprocessor, and a select switch connected to a...
7624220 Multisectional bus in radio base station and method of using such a radio base station  
A communication system has a monitor, memory and one or more resources. The memory is connected to the monitor by a bus and stores tasks and data. Each of the resources is connected to the monitor...
7613928 Flash device security method utilizing a check register  
A security method for preventing accidental or unauthorized writes to a flash memory. According to one embodiment of the present invention, a BIOS program stored in a flash memory array generates...
7610421 Bus request control circuit  
A bus request control circuit provided in a signal processing circuit having a higher priority in an arbitration circuit includes a request signal transmitting section which transmits a request...
7609540 Serial bus controller using nonvolatile ferroelectric memory  
A serial bus controller using a nonvolatile ferroelectric memory is provided. The memory controller structure using a nonvolatile ferroelectric register enables control of variable access time...
7609713 Associating a signal measurement with a communication device on a network  
A signal measured on a network is associated with one of a plurality of communication devices connected to the network. The designation address of an active communication device that is scheduled...
7603478 Displaying routing information for a measurement system  
Computer-implemented system and method for presenting routing information in a measurement system. A meta-routing tool receives user input specifying a device, then retrieves a topography...
7598948 System and method of detecting rotated displays  
A system for adjusting display data orientation. The system includes graphics circuitry to send and receive control signals over a set of control lines. The exchange of control signals is governed...
7594042 Effective caching mechanism with comparator coupled to programmable registers to store plurality of thresholds in order to determine when to throttle memory requests  
A system includes a plurality of bus masters that generate direct memory access requests to access a protected memory device. Before granting the access, the system checks for memory protection...
7594074 Storage system  
To provide a storage system with a cost/performance meeting the system scale, from a small-scale to a large-scale configuration. In the storage system, protocol transformation units and data...
RE40921 Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system  
A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if...
7590140 Method for addressing the participants of a bus system  
In the method for addressing the participants of a bus system, the central control unit connects the bus line to one potential of the operating voltage, while each participant tries to pull the...
7587523 Distributed systems for determining card status  
The master/slave arbitration process includes a voting process that allows cards within the system to use voting to determine the health of each of the individual cards. The voting process thereby...
7580811 Medical data communication interface monitoring system  
A system maintains statistics on DICOM interfaces that include for each interfaced Application Entity, the number, timing and types of DICOM failures, number and timing of broken network...
7565467 USB hub, USB-compliant apparatus, and communication system  
A USB hub according to an embodiment of the invention includes: a USB upstream port unit for inputting/outputting data in accordance with a USB protocol; a wireless upstream port unit for...
7565420 Method for initializing a distributed software architecture and an electronic system  
The present invention relates to a method for initializing a distributed software architecture as well as an electronic system. A control module for a network function is made available in the...
7562143 Managing escalating resource needs within a grid environment  
A job is submitted into a first selection of resources in a grid environment from among a hierarchy of discrete sets of resources accessible in the grid environment. Discrete sets of resources may...
7558944 Microcomputer  
A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and...
7552257 Data transmission device with a data transmission channel for the transmission of data between data processing devices  
The present invention provides a data processing apparatus having at least one dedicated data processing device (10) of a first type, a central data processing device (4) for controlling dedicated...
7552289 Method and apparatus for arbitrating access of a serial ATA storage device by multiple hosts with separate host adapters  
An adapter unit operative to support access of an SATA storage device by a plurality of hosts associated with separate host adapters. The adapter unit includes a multiplexer coupled to an arbiter....
7549009 High-speed PCI interface system and a reset method thereof  
A high-speed PCI interface system with reset function and a reset method thereof are provided. The interface system comprises a host controller chipset, at least one high-speed PCI device and at...
7543094 Target readiness protocol for contiguous write  
A method of performing contiguous write transactions on a processor bus according to an embodiment of the present invention includes detecting, by a bus agent, a request for a write cycle,...
7529861 Peripheral switching device and a peripheral switching control device  
A peripheral switching device includes an ownership switch request receiver unit configured to receive an ownership switch request for requesting to assign a peripheral to an operating system; an...
7529268 Multi-point electronic control system protocol  
A generic software protocol allows communication between multiple devices within an electronic control system as well as between an electronic control system and an external monitoring device. The...
7523268 Reducing number of rejected snoop requests by extending time to respond to snoop request  
A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if...
7519774 Data processor having a memory control unit with cache memory  
The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external...
7519751 Method of generating an enable signal of a standard memory core and relative memory device  
A memory device is configured for communicating with one of two different serial protocols, respectively an LPC or an SPI protocol, as well as with a parallel communication protocol through a...
7519752 Apparatus for using information and a count in reissuing commands requiring access to a bus and methods of using the same  
In a first aspect, a first method of reissuing a command involving bus access is provided. The first method includes the steps of (1) storing information associated with commands that are to be...
7516313 Predicting contention in a processor  
In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction,...
7512729 Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latency  
A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter...
7508981 Dual layer bus architecture for system-on-a-chip  
A dual layer bus architecture for a system-on-a-chip (SOC) is disclosed. The bus architecture comprises a main bus adapted to connect a microprocessor, an image capture module, and a dual master...
7506085 System and method for sending data across a bus cable having in-band and side-band signal conductors  
A method and apparatus for sending data. One exemplary embodiment may be a method comprising sending a data rate synchronization pulse from drive controller in a computer system to a storage...
7500042 Access control device for bus bridge circuit and method for controlling the same  
An access control device having a number-of-waits setting circuit determining a wait periodicity corresponding to an operating speed of peripheral devices connected to a second bus according to an...
7493425 Method, system and program product for differentiating between virtual hosts on bus transactions and associating allowable memory access for an input/output adapter that supports virtualization  
A method, system and computer program product that allows a System Image within a multiple System Image Virtual Server to maintain isolation from the other system images while directly exposing a...
7487281 Computer system to control the data transfer between a memory and a peripheral device connected to a CPU via a bus  
In a computer system that includes a memory, a peripheral device to which an address overlapping with a part of an address space assigned to the memory is assigned, a CPU for sending a signal...
7486637 Wireless communication method and system for efficiently managing paging windows and data messages  
A wireless communication method and system for efficiently managing paging windows and data messages. The wireless communication system includes at last one network and a plurality of user...