Sign up

AcclaimIP-ad

Match Document Document Title
8122175 Opportunistic transmission of software state information within a link based computing system  
A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the...
8112566 Methods and apparatuses for processing I/O requests of data storage devices  
Methods and apparatuses for processing input and/or output requests for data storage devices are disclosed. Method embodiments generally comprise receiving a number of requests, wherein at least...
8108581 Information processing apparatus  
According to one embodiment, an information processing apparatus including a suspension/resume function includes a bus controller which controls a bus capable of transmitting data at a first...
8094677 Multi-bus structure for optimizing system performance of a serial buffer  
A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a...
8074004 Electronic device for contention detection of bidirectional bus and related method  
An electronic device of detecting contention of a bidirectional bus for avoiding failing to drive a bidirectional bus due to bus contention includes: an output terminal, an input terminal and a...
8069282 SD switch box in a cellular handset  
A method for arbitrating between a host device and a cellular base band mode for use of a shared SD storage, including requesting, by a cellular base band modem from a host device, access to an SD...
8065457 Delayed memory access request arbitration  
A method for delayed memory access request arbitration includes dispatching a first memory access request to a memory controller and dispatching a second memory access request to the memory...
8055817 Efficient handling of queued-direct I/O requests and completions  
Computer program products and methods for efficient handling of queued-direct input/output (QDIO) requests and completions at an adapter in communication with an I/O device are provided. A method...
8051232 Data storage device performance optimization methods and apparatuses  
Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally...
8051233 Method and system for addressing a plurality of ethernet controllers integrated into a single chip which utilizes a single bus interface  
A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet...
8045407 Memory-write timing calibration including generation of multiple delayed timing signals  
A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control...
8046514 Broadcasting data across a bus in which data transmission can be delayed if a snooping device is not ready to receive  
A system and method of broadcasting data to multiple targets across a system bus, such as the peripheral component interconnect (PCI) bus, that does not normally support broadcast transfers, in...
8041870 Method and apparatus for dynamically granting access of a shared resource among a plurality of requestors  
An arbiter in a communication system including a plurality of request shapers in communication with a plurality of requestors. Each request shaper is configured to receive a request for access to...
8032715 Data processor  
The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external...
8032676 Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device  
Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Rate logic may couple to the...
8011006 Access controller and access control method  
An access controller controls access to control target resources by a program. The access controller includes a function access detection unit and a resource access control unit. The function...
8010723 Safety controller with data lock  
The present invention relates to a SPC comprising at least one data processing means for realizing a first data channel 1 and a second data channel 2, and comprising a data transmission means 3...
8009173 Rack interface pod with intelligent platform control  
Rack Interface Pods can be augmented with non-KVM (keyboard, video and mouse) functionality that can enable greater analysis of the state of the computer to which the RIP is attached. A RIP can be...
8006013 Method and apparatus for preventing bus livelock due to excessive MMIO  
The disclosure relates to a method and apparatus to efficiently address livelock in a multi-processor system. In one embodiment, the disclosure is directed to a method for preventing a system bus...
8006000 Bridge, processor unit, information processing apparatus, and access control method  
There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter 14 includes an...
7999801 System and method of detecting rotated displays  
A system for adjusting display data orientation. The system includes graphics circuitry to send and receive control signals over a set of control lines. The exchange of control signals is governed...
7996626 Snoop filter optimization  
A snoop filter optimization system includes one or more subsystems to operate a snoop filter, determine information that that affects operation of the snoop filter, and adjust operation of the...
7987398 Reconfigurable device  
Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks,...
7987488 System for transmitting and receiving data  
A system for transmitting and receiving image and audio data that is information on any of image and audio has a transmission apparatus and a reception apparatus. The transmission apparatus...
7979615 Apparatus for masked arbitration between masters and requestors and method for operating the same  
An apparatus is disclosed for handling multiple requestors desiring access to a resource. The apparatus includes a plurality of masters and a plurality of arbitrators. Each arbitrator is assigned...
7979616 System and method for providing a configurable command sequence for a memory interface device  
A system and method for providing a configurable command sequence for a memory interface device (MID). The system includes a MID intended for use in a cascade interconnect system and in...
7975086 Apparatus for real-time arbitration between masters and requestors and method for operating the same  
A circuit is provided for handling multiple requestors desiring access to a resource. The circuit includes a plurality of arbitrators and a plurality of masters. Each master is assigned to a...
7970969 Method for communication on a multidrop bus of a magnetic resonance system  
In a method of communication on a multidrop bus of a magnetic resonance system, an adaptive protocol script for telegrams on the multidrop bus is used, that implements adaptive protocol matching...
7970970 Non-blocking address switch with shallow per agent queues  
In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage...
7966438 Two-wire communications bus system  
A low-cost, two-wire, half-duplex high speed powered communications bus having a master/controller and one or more slave/sensor/interface units. The master/controller may have a current-limited...
7962677 Bus access moderation system  
A method, programmed medium and system are provided in which system bus traffic is moderated with real-time data. The Operating System (OS) is enabled to get information from the firmware (FW) to...
7949811 Method and device for creating a time schedule for transmitting messages on a bus system  
A method for creating a time schedule for transmitting messages on a bus system (bus schedule), the time schedule being created by using a genetic algorithm.
7949817 Adaptive bus profiler  
An adaptive bus profiler is described. In embodiment(s), data traffic that is communicated on an adaptive bus can be monitored, and projected data traffic that is scheduled for communication via...
7944937 Data transmission apparatus efficiently using network resources  
A data transmission apparatus connecting to a network consisted of a plurality of data transmission apparatuses comprises a disconnecting device that disconnects a connection established between a...
7929539 Multiple queue pair access with a single doorbell  
A method for controlling access by processes running on a host device to a communication network includes assigning to each of the processes a respective doorbell address on a network interface...
7930456 Data packet arbitration system  
A data packet arbitration system for routing data transfers from a plurality of clients to a data transmission line is described. The system includes multiple arbitration stages for transferring...
7921231 Discovery of electronic devices utilizing a control bus  
Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving...
7921249 Weakly ordered processing systems and methods  
The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master...
7917676 Efficient execution of memory barrier bus commands with order constrained memory accesses  
The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master...
7917675 Method and apparatus for interconnecting modules  
An industrial process control apparatus and method that includes a number of processors and a number of input/output modules. Each processor is connected to a plurality of the input/output modules...
7913011 Method and apparatus for employing a second bus controller on a data bus having a first bus controller  
A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting...
7913007 Systems, methods, and computer readable media for preemption in asynchronous systems using anti-tokens  
Systems, methods, and computer program products for preemption in asynchronous systems using anti-tokens are disclosed. According to one aspect, configurable system for constructing asynchronous...
7911819 Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules  
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being...
7913010 Network on chip with a low latency, high bandwidth application messaging interconnect  
A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106),...
7904624 High bandwidth split bus  
A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing...
7899941 Displayport I2C speed control  
Circuits, methods, and apparatus that allow a DisplayPort compatible host device to control data transactions over an I2C bus when communicating with a legacy monitor. One example includes an...
7895380 Communication protocol for sharing memory resources between components of a device  
In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an...
7890663 Identifying nodes in a ring network  
Methods are provided for determining a master node on a ring network. According to one embodiment, a first node on the ring network initiates circulation of an arbitration token by (i) determining...
7889657 Signaling completion of a message transfer from an origin compute node to a target compute node  
Signaling completion of a message transfer from an origin node to a target node includes: sending, by an origin DMA engine, an RTS message, the RTS message specifying an application message for...
RE42134 Process for generating a serial number from random numbers  
A process for generating a serial number from a random number is suitable for being used on a device that uses serial number in a bus. First, this process generates a serial number for use from a...