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7921231 Discovery of electronic devices utilizing a control bus  
Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving device...
7921249 Weakly ordered processing systems and methods  
The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master...
7917676 Efficient execution of memory barrier bus commands with order constrained memory accesses  
The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master...
7917675 Method and apparatus for interconnecting modules  
An industrial process control apparatus and method that includes a number of processors and a number of input/output modules. Each processor is connected to a plurality of the input/output modules...
7913011 Method and apparatus for employing a second bus controller on a data bus having a first bus controller  
A method for employing a second bus controller on a data bus having a first bus controller including: (a) recording appearances of predetermined character groups on the data bus; (b) noting...
7913007 Systems, methods, and computer readable media for preemption in asynchronous systems using anti-tokens  
Systems, methods, and computer program products for preemption in asynchronous systems using anti-tokens are disclosed. According to one aspect, configurable system for constructing asynchronous...
7911819 Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules  
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being...
7913010 Network on chip with a low latency, high bandwidth application messaging interconnect  
A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), ...
7904624 High bandwidth split bus  
A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing...
7899941 Displayport I2C speed control  
Circuits, methods, and apparatus that allow a DisplayPort compatible host device to control data transactions over an I2C bus when communicating with a legacy monitor. One example includes an...
7895380 Communication protocol for sharing memory resources between components of a device  
In a device, such as a cell phone, memory resource sharing is enabled between components, such as integrated circuits, each of which has memory resources. This may be accomplished by providing an...
7890663 Identifying nodes in a ring network  
Methods are provided for determining a master node on a ring network. According to one embodiment, a first node on the ring network initiates circulation of an arbitration token by (i) determining...
7889657 Signaling completion of a message transfer from an origin compute node to a target compute node  
Signaling completion of a message transfer from an origin node to a target node includes: sending, by an origin DMA engine, an RTS message, the RTS message specifying an application message for...
RE42134 Process for generating a serial number from random numbers  
A process for generating a serial number from a random number is suitable for being used on a device that uses serial number in a bus. First, this process generates a serial number for use from a...
7882281 SAS reference Phys for virtualization and traffic isolation  
Enabling virtualization in a SAS expander is disclosed. For each SAS address to be virtualized through one or more physical or virtual Phy, a reference Phy associated with each SAS address is...
7865646 Sharing of functions between an embedded controller and a host processor  
An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables...
7861042 Processor acquisition of ownership of access coordinator for shared resource  
A processor of an apparatus in an example upon a failure of an earlier attempt to directly acquire ownership of an access coordinator for a resource shared with one or more additional processors,...
7856520 Control bus for connection of electronic devices  
A method and apparatus for a control bus for connection of electronic devices. An embodiment of a method includes coupling a transmitting device to a receiving device, including connecting a...
7849245 Bus-based communication system  
A communications bus operates using transition coding, for example NRZI coding, with transition-dominant signalling. That is, when the signal takes a first binary value, binary “1”, the com...
7840736 Bus communication enumeration  
Provided are a method, system, and program for initializing a processor of a computer system, to enumerate a remote bus and remote devices coupled to the remote bus, as operating components of the...
7840735 Can system  
A CAN system includes a plurality of CAN modules and a CAN bus connecting the CAN modules. In at least one embodiment, a filter device is mounted between at least one CAN module and the CAN bus, by...
7840723 System and method for maintaining and accessing information regarding virtual storage devices  
Systems, methods, apparatus and software can make use of standard input/output (I/O) interface commands to make information about virtual storage devices available to clients of those virtual...
7830172 Accessing user registers in an integrated circuit  
Access is provided to user registers of a user design implemented on an integrated circuit (IC). A memory of the IC is initialized with instructions, and a portion of the programmable logic and...
7822898 Method and apparatus for border node behavior on a full-duplex bus  
A method and apparatus relating to the behavior of border nodes within a high performance serial bus system is disclosed. A method for determining and communicating the existence of a hybrid bus is...
7818511 Reducing number of rejected snoop requests by extending time to respond to snoop request  
A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of ...
7814249 Apparatus to recognize memory devices  
An apparatus to recognize memory devices, the apparatus including a plurality of slaves having the same fixed address, a master controller to supply power to the slaves and to output a signal to...
7809863 Monitor processor authentication key for critical data  
A command generating and monitoring system includes a command processor configured to determine a command data set from a command input. A monitoring processor is coupled to the command processor...
7805549 Transfer apparatus and method  
There is provided a transfer apparatus having a bridge that transfers a transaction between a first and a second bus, and a data transfer unit that performs a data transfer by DMA between the first...
7804890 Method and system for response determinism by synchronization  
A discussion of improving integrated device deterministic response to test vectors. For example, limiting the transmission delay for an integrated device's response within known bounds by...
7805578 Data processor apparatus and memory interface  
A data processor apparatus and memory interface comprises a memory, a plurality of memories, an interface for controlling access to the memories by a device, and an identifier identifying at least...
7797472 Method and apparatus for providing overlapping defer phase responses  
A multiprocessor system in which a defer phase response method is utilized that allows for a deferring agent to interrupt the normal flow of bus transactions once it gains control of system...
7793008 AMBA modular memory controller  
A system comprising a plurality of controller circuits, a plurality of line buffer circuits and an arbiter. The plurality of control circuits may each be configured to store data. The plurality of...
7788432 System for performing a serial communication between a central control block and satellite components  
The various embodiments described herein relate to a system for performing a serial communication between a central control block and a plurality of satellite components within a semiconductor...
7783915 Automation system and a method and input/output assembly therefore  
Disclosed is an automation system (1) for executing safety-relevant automation functions. Said automation system (1) comprises one or several control componentries (10) and one or several...
7783827 Data processor having a memory controller with cache memory  
The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external...
7774531 Allocating processor resources during speculative execution using a temporal ordering policy  
One embodiment provides a system which uses a temporal ordering policy for allocation of limited processor resources. The system starts by executing instructions for a program during a...
7774356 Method and apparatus for application state synchronization  
A method and an apparatus that synchronize an application state in a client with a data source in a backend system in an asynchronous manner are described. A response is sent to the client based on...
7774794 Method and system for managing bandwidth in a virtualized system  
A method of improving USB device virtualization to prevent bus bandwidth from being over allocated when isochronous USB devices are attached to multiple virtual machines by attaching a dummy device...
7774529 Bus communication apparatus that uses shared memory  
Bus transfer efficiency is improved in bus communication that uses a shared memory, based on a communication origin master 101 selectively using an arbitration completion notification signal and a...
7774532 Processing device, failure recovery method therefor, and failure restoration method  
A processing device includes a processor which executes first and second pieces of control software in a memory to perform processing, and a device 1 having a plurality of SLOTs 1 to 8 to...
7774511 Addressing multiple devices on a shared bus  
Assigning addresses to legacy sharing at least one signal line with a plurality of client devices. Each of the devices includes a number of I/O pins selected ones of which are connected to the at...
7769932 Bitwise arbitration on a serial bus using arbitrarily selected nodes for bit synchronization  
A plurality of nodes are coupled via a serial data bus A transition from a first state to a second state is repeatedly transmitted onto the bus from a node arbitrarily selected from the plurality...
7770149 Semiconductor device, system for performing data processing, and method for performing communication between software framework and plurality of software modules  
A framework registers the entry names of entry interfaces respectively included in modules. The framework acquires operation names (static entries) of operation interfaces included in the module by...
7769922 Processing system streaming data handling system and stream register  
A processing system for accessing first and second data types. The first data type is data supplied from a peripheral and the second data type is randomly accessible data held in a data memory. The...
7769934 Master and slave side arbitrators associated with programmable chip system components  
Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system....
7765349 Apparatus and method for arbitrating heterogeneous agents in on-chip busses  
A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request...
7752341 Programmable controller and communication unit therefor  
A programmable controller includes a CPU unit, a communication unit and peripheral units connected together through an internal bus. The communication unit has a bus master function, including a...
7751850 Single chip multimode baseband processing circuitry with a shared radio interface  
A multimode communication integrated circuit comprising baseband processing circuitry with a shared radio interface. Various aspects of the present invention may comprise a processor module adapted...
7752366 Non-blocking address switch with shallow per agent queues  
In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage...
7747803 Device, system, and method of handling delayed transactions  
Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject...