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6487620 Combined low speed and high speed data bus  
A method and system for communicating at least two data transfers on a common bus. Data is communicated between a simple device and a system processor or system connector via the common bus at a...
6480915 Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release  
Serialization of global operations within a multiprocessor system is achieved utilizing a single token, requiring a bus master to acquire the token for completion of each individual global...
6480916 Information processing method and system for composite appliance  
A generated job is divided in units of pages, and devices for executing processes for the respective pages are assigned. While the processing results of the devices for pages as processing units...
6480926 Bus controlling system  
In a system including a plurality of rotatable media type memory devices and disk array storage including in a redundant configuration a plurality of controllers each including a disk array...
6480909 Computer system for selectively connecting IEEE 1394 internal peripheral devices to either 1394 physical layer ports or 1394 external ports in response to control signal  
An apparatus and a method for connecting peripheral devices to each other in a computer supporting IEEE1394 are provided. An apparatus for connecting peripheral devices in a computer supporting...
6477596 Bus controlling method and apparatus for delaying activation of a bus cycle  
With respect to design regarding a bus cycle, it has been necessary to consider a data conflict, if an output disable time of a device is long. A bus controlling unit is installed in a processor....
6477609 Bridge state-machine progression for data transfers requested by a host bus and responded to by an external bus  
An expansion module for a Handspring Visor (which conforms to the Springboard bus specification) includes a multi-master AMBA Advanced System Bus (ASB). Optionally, an Arm7 processor is attached...
6470407 Method for arbitrating interrupt priorities among peripherals in a microprocessor-based system  
A method for arbitrating interrupt priorities among peripherals in a microprocessor-based system includes providing a bus which connects a central processing unit (CPU) to a plurality of...
6463490 Dual data rate transfer on PCI bus  
The invention provides a method of performing data transfers on a PCI bus between a PCI bus master and a selected device. Wherein, there is a request signal and a grant signal on the PCI bus for a...
6463540 Securing method for computer bus devices  
The invention relates to a security lock for devices connectable to a computer bus. The devices receives from the computer information as to the owner of the computer, and compares the information...
6463488 Apparatus and method for testing master logic units within a data processing apparatus  
The present invention provides a data processing apparatus and method of testing a master logic unit within a data processing apparatus, the data processing apparatus comprising one or more master...
6463495 Command and control infrastructure for a computer system using the computer's power rail  
A method and system of intrachassis computer component command and control. The existing power rail is used as network connectivity. Further, the CEBus standard (or a CEBus standard modified for...
6460101 Token manager for execution of global operations utilizing multiple tokens  
Serialization of global operations within a multi-processor system is achieved utilizing a plurality of tokens each permitting completion of a single global operation, requiring a bus master to...
6460096 Automatic serial bus transmission sequencer  
A messaging system for a vehicle is disclosed. The messaging system includes a primary controller for transmitting and receiving information. The primary controller generates an array of data...
6460100 Bus snooper for SMP execution of global operations utilizing a single token with implied release  
Only a single snooper queue for global operations within a multiprocessor system is implemented within each bus snooper, controlled by a single token allowing completion of one operation. A bus...
6457074 Direct memory access data transfers  
A digital system has a host processor 200 with a bus controller 210 and peripherals 220(0)-220(31) interconnected by an interconnect bus 230. 32 peripherals are share a common strobe line (nSTROBE...
6457085 Method and system for data bus latency reduction using transfer size prediction for split bus designs  
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch,...
6457078 Multi-purpose bi-directional control bus for carrying tokens between initiator devices and target devices  
A communication protocol is implemented by a control bus using multi-purpose bi-directional signal lines. The bi-directional signal lines provide a single control path shared among any number of...
6457081 Packet protocol for reading an indeterminate number of data bytes across a computer interconnection bus  
A read request is sent from a source to a target over a requesting all available data. The requester does not know the amount of data available. The response to the read request includes the...
6457079 Communication apparatus with means for allocating alternate designation information to each function unit, and communication system with said two communication apparatuses  
A communication apparatus is provided for communicating with further communication apparatuses which are connected with the communication apparatus, and for allowing one of a plurality of function...
6453373 Method and apparatus for differential strobing  
A method for ensuring proper strobe pre and post driving between a first data transfer and a second data transfer in a microprocessor system. The method includes generating a first strobe signal...
6453376 Method for implementing scheduling mechanisms with selectable resource modes  
A method for implementing scheduling mechanisms with selectable resource modes comprises at least one resource characterization set that includes a plurality of resource characterizations that...
6449671 Method and apparatus for busing data elements  
A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction...
6449672 PCI device arbiter  
An arbiter arbitrates between PCI agents within an ASIC. The ASIC interfaces with an external PCI bus. In operation, the arbiter receives request signals from the PCI agents, and in response...
6442631 Allocating system resources based upon priority  
A computer system is implemented according to the invention when priority information is included with a bus transaction. Instead of processing bus transactions on a first-come-first-served basis,...
6438624 Configurable I/O expander addressing for I/O drawers in a multi-drawer rack server system  
A method of configuring a data communications system, by changing a default communications address of a logic component to a first assigned address, and connecting the logic component to a...
6438633 System for providing deterministic performance from a non-deterministic device  
A system for providing deterministic performance from a non-deterministic device comprises one or more nodes that perform isochronous and/or non-isochronous data transfer operations onto an...
6434650 Apparatus and method for multiplexing bi-directional data onto a low pin count bus between a host CPU and co-processor  
An apparatus and method for communication between a host CPU and a security co-processor are disclosed, in which a bus having a bi-directional data and command bus, a bi-directional control line,...
6430636 Method and system for a physical bus selector  
A communication interface device with a card chassis capable of holding a number of electronic equipment or circuit cards. The card chassis provides a communication backplane that provides a...
6430642 Methods and apparatus for prioritization of access to external devices  
According to the present invention, an apparatus for prioritizing access to external devices includes a request queue suitably arranged to store any number of requesting device requests of the...
6430637 Method for multiplexing bus interfaces on a computer expansion bus  
A computer system includes a processor/PCI bus bridge that couples a processor bus to a relatively high-speed expansion bus, such as a PCI bus and a PCI extension bus. The PCI extension bus is...
6425033 System and method for connecting peripheral buses through a serial bus  
A Wide Area Serial PCI system for connecting peripheral devices to a computer. The WASP system includes a host computer system connected through a serial bus to a remote device. The serial bus can...
6421751 Detecting a no-tags-free condition in a computer system having multiple outstanding transactions  
A computer system includes a pipelined communication link on which pipelined transactions are identified by a tag. A finite number of tags are available. The computer system detects where all the...
6418511 Large capacity data storage systems using redundant buses  
A data storage system wherein a host computer is coupled to a bank of disk drives through a system interface. The system interface includes a memory having a high address memory section and a low...
6411218 Priority-encoding device selection using variable arbitrary rankings  
In the context of a bus-mastering system, a device selector selects the device to control the bus by assigning “combined” priority values to the devices and selecting the device with the highest...
6408347 Integrated multi-function adapters using standard interfaces through single a access point  
Methods and systems are provided for communicating to multiple functions on a single adapter device over an external communications bus, where the external communications bus is configured so as...
6405271 Data flow control mechanism for a bus supporting two-and three-agent transactions  
A data flow control mechanism for a bus supporting two- and three-agent transactions includes a control logic to place an indication of a request onto a computer system bus. The agent placing the...
6401145 Method of transferring data using an interface element and a queued direct input-output device  
A method of transferring data in a network computing environment having a controlling program and a main storage in processing communication with an interface element including one or more...
6393506 Virtual channel bus and system architecture  
A processor system includes an on-chip, split-transaction bus with independent address/control and data buses. Arbitration and bus acquisition protocols are performed on the address/control bus....
6393505 Methods and apparatus for data bus arbitration  
A data bus arbitration system is disclosed including a bus status monitor which is coupled to a data bus and generates a bus status signal for use by an arbiter. The arbiter is coupled to a number...
6389492 Apparatus for flexibly allocating request/grant pins between multiple bus controllers  
One embodiment of the present invention provides an apparatus that flexibly allocates I/O pins used for bus grant signals between bus controllers. The apparatus includes a semiconductor chip...
6385680 Method for flexibly allocating request/grant pins between multiple bus controllers  
One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates...
6374244 Data transfer device  
A data transfer device for transferring plural asynchronous data processed and input/output at different rates includes a memory for storing data. The memory is shared between first through fourth...
6374318 Filter-circuit for computer system bus  
A filter circuit for filtering bus accesses from a computer bus (such as e.g. a bus conforming to the PCI standard) to a group of devices operably coupled to the computer bus in a computer system....
6374319 Flag-controlled arbitration of requesting agents  
A method and an system are provided for servicing a plurality of agents requesting access to a bus. The agents are arranged in a hierarchical order of groups, each having first and second pairs of...
6374317 Method and apparatus for initializing a computer interface  
According to one embodiment, a computer system includes a first hub agent and a hub interface coupled to the first hub agent. The first hub agent is adaptable to sample the hub interface in order...
6363428 Apparatus for and method of separating header information from data in an IEEE 1394-1995 serial bus network  
An apparatus for and method of separating protocol header information from content data in an IEEE 1394-1995 serial bus network. A receiving node receives isochronous data packets from a...
6363446 Method for selectively encoding bus grant lines to reduce I/O pin requirements  
One embodiment of the present invention provides a method for selectively encoding bus grant lines to reduce I/O pin requirements. The method includes receiving a number of grant lines emanating...
6363439 System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system  
A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a...
6363445 Method of bus arbitration using requesting device bandwidth and priority ranking  
A bus arbitration regulates access to a common bus by a plurality of devices by assigning each device a priority rank. A current weighted bandwidth of each device is set equal to a desired...