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6598140 Memory controller having separate agents that process memory transactions in parallel  
A memory controller has separate memory controller agents that process memory transactions in parallel. A memory controller in accordance with the present invention includes a plurality of memory...
6598111 Backplane physical layer controller  
A system includes a serial bus 330, at least a first portion of which is formed on a circuit board. A first physical layer controller 322 is coupled to the first portion of serial bus 330. This...
6594718 Arbitration scheme for equitable distribution of bandwidth for agents with different bandwidth requirements  
A device for arbitrating access to a resource by a plurality of agents includes logic configured to associate requesting ones of the agents with access tokens. The number of the access tokens...
6591294 Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6590907 Integrated circuit with additional ports  
An integrated circuit which has a packet router to which a plurality of functional modules are connected by respective ports is described. One of the ports acts as a socket port for an expansion...
6586968 Programmable bit ordering for serial port  
An order in which bits for serial data are transmitted or received by a first device, integrated circuit (IC) or logic, is programmable to be either from most significant bit (MSB) to least...
6587905 Dynamic data bus allocation  
A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master...
6584103 Packet communication apparatus provided with manager means for managing packet labels  
A packet communication apparatus is provided for transmitting a packet with a label for distinguishing each packet to each destination apparatus, and receiving a response packet with the same...
6584523 Device for organizing the access to a memory bus  
This invention relates to a device for organizing access to a bus connecting a memory to at least two entities asynchronous binary signals representing requests for access to the bus. The device...
6584528 Microprocessor allocating no wait storage of variable capacity to plurality of resources, and memory device therefor  
A microprocessor includes a first bus and a second bus capable of operating simultaneously, a single port memory divided into a plurality of banks, a bus switch circuit provided between the...
6581124 High performance internal bus for promoting design reuse in north bridge chips  
In an example embodiment, an apparatus providing communication in a computer system, comprises, a plurality of modules each having a master port and a slave port A secondary bus is shared between...
6581115 Data processing system with configurable memory bus and scalability ports  
A data processing system with configurable processor chip buses. The processor chip is designed with a plurality of extended buses of which a number are configurable buses (i.e., capable of being...
6581116 Method and apparatus for high performance transmission of ordered packets on a bus within a data processing system  
A method for transmitting ordered packets on a bus within a data processing system is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. The bus...
6578126 Memory system and method of using same  
A memory system and method of using same are provided. In one embodiment of the present invention, a novel memory operation protocol may be used to facilitate the execution of memory operations in...
6578100 Storage system having plural buses  
A storage system to be connected to a large-scale computer includes a plurality of first logical units connected to a host device, a plurality of second logical units connected to a storage...
6578097 Method and apparatus for transmitting registered data onto a PCI bus  
A method and apparatus for transmitting registered data onto a PCI bus is provided, which can reduce the delay time of manipulating the outgoing signals without greatly increasing the circuit...
6577905 Apparatus and method for providing a transient port  
An apparatus and method for providing a transient connection port are provided. Further, an apparatus and method for switching between a permanent connection port and a transient connection port...
6564275 Electronic switching device for a universal serial bus interface  
The present invention provides an electronic switching device for a universal serial bus (USB) interface, which can connect several different electronic devices each having a universal serial bus...
6560662 Time-out processing method and apparatus for SCSI system as well as recording medium on which program is recorded  
The invention provides a time-out processing method and apparatus for a SCSI system by which an appropriate time-out time for each initiator can be set in a target without the necessity for...
6557059 Parallel peripheral interface  
The invention provides apparatus for the transfer of data/command between a master controller and one or more client controllers. The apparatus in accordance with the invention includes a...
6557069 Processor-memory bus architecture for supporting multiple processors  
An internal processor/memory bus contains an address portion for transmitting addresses and commands, having a series of hierarchical uni-directional links between processors and local repeaters...
6557068 High speed peripheral interconnect apparatus, method and system  
A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a...
6553430 Computer system implementing flush operation  
A computer system is presented which implements a “flush” operation providing a response to a source which signifies that all posted write operations previously issued by the source have been...
6549961 Semaphore access in a multiprocessor system  
Access control to protected resources in a multiprocessor system is implemented without additional use of the processor bus. A bridge interconnects each processor with shared resources. The bridge...
6549964 Delayed transaction method and device used in a PCI system  
A delayed transaction method and system to handle multiple delayed transactions in a PCI system is disclosed. When the responder accepts a first and second request from an initiator but can not...
6542947 Data bus for serial data transmission  
A data bus for serial bus transmission between apparatus which are capable of transmitting and/or receiving data via the data bus, recessive and dominant states being present on the data bus and...
6535519 Method and apparatus for data sharing between two different blocks in an integrated circuit  
An integrated circuit that includes an improved architecture that reduces the interface between different blocks by minimizing the wire connections between the two blocks. Specifically, the two...
6532507 Digital signal processor and method for prioritized access by multiple core processors to shared device  
A system and signal processing method, in which at least two processors have prioritized, shared access to one or more devices connected along a bus. In preferred embodiments, a fast processor is...
6532508 Control system for controlling safety-critical processes  
The present invention describes a control system for controlling safety-critical processes. The control system has a first control unit for controlling a safety-critical process and at least one...
6516368 Bus master and bus snooper for execution of global operations utilizing a single token for multiple operations with explicit release  
In response to a need to initiate one or more global operations, a bus master within a multiprocessor system issues a combined token and operation request in a single bus transaction on a bus...
6515515 Bidirectional data transfer path having increased bandwidth  
A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other....
6513078 Data transfer control apparatus, data transfer control system and data transfer control method  
Data transfer mode between a plurality of circuit mod modules connected to a data bus is dynamically switched between a time division, space-division multiplexing and so forth for improving data...
6513074 SCSI bus intelligent listening device and method  
An intelligent bus listening device, and a method which may be implemented as a computer program product, listens to SCSI commands on a first SCSI bus of a SCSI system via a listening connection...
6513080 High speed bus system and method for using voltage and timing oscillating references for signal detection  
A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate...
6513094 ROM/DRAM data bus sharing with write buffer and read prefetch activity  
Briefly, a processor-based device, such as a microcontroller, provides a data bus that is shared by both non-volatile memory and volatile memory. The processor-based device also provides...
6513089 Dual burst latency timers for overlapped read and write data transfers  
The present invention discloses a method and system for managing independent read and write buses by dividing the pending read and write request signals and the read and write request priority...
6513081 Memory device which receives an external reference voltage signal  
A memory device and a method of operation of the memory device. The memory device includes an array of memory cells and a reference voltage input terminal to receive an external reference voltage....
6507612 Bus access controller  
A bus control circuit of the present invention, which is connected to a request source through a bus, includes a first element which detects a fault of one part of the bus when data is sent...
6507880 Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens  
In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined...
6507878 Bus snoop control circuit  
A bus snoop control circuit of the present invention, which is connected to a bus, includes a first circuit which determines whether or not the bus snoop control circuit snoops data based on an...
6505263 Bus controller operating code in system memory  
A computer system having bus controller operating code stored in a non operating system managed, extended portion of system memory. In one example, the operating code is executed by a bus...
6505265 Bus arbitration system with changing arbitration rules  
A bus arbitration system uses different arbitration rules at different times, by periodically changing the priority order of the bus masters; by masking further bus requests from a particular bus...
6499066 Method and apparatus for using fibre channel test extended link service commands for interprocess communication  
The present invention provides fiber channel networks the ability to use extended link service commands to convey implementation dependent information between ports.
6496583 Digital data transfer apparatus and method  
A converting processing block (4B/5B CONVERTER & ARB. SIGNAL CONVERTER) functions as a 4 bit/5 bit converting unit for performing 4 bit/5 bit conversion of data and as an arbitration signal...
6496740 Transfer controller with hub and ports architecture  
The transfer controller with hub and ports (TCHP) performs the task of communication throughout an entire system in a centralized function. A single hub (435) tied to multiple ports (440, 447,...
6496890 Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters  
A shared bus hang prevention and recovery scheme for a data communication system is provided, where a shared bus is connected to a plurality of bus masters and corresponding slaves and located...
6493771 Method of sharing a communication port  
A method for controlling a communication port of a computer by an application running on the computer is disclosed. The application interfaces with an external device through a cable connected to...
6493775 Control for timed access of devices to a system bus  
A bus control device having a plurality of devices such as a processor or a DMAC which can be a bus master accessing a system bus. When the processor transfers data to a memory or a processing...
6490644 Limiting write data fracturing in PCI bus systems  
A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous...
6487621 Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycle  
An architecture, system and method are provided for efficiently transferring data across multiple processor buses. Cache coherency is maintained among cache storage locations within one or more of...