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6785753 Method and apparatus for response modes in pipelined environment  
A pipelined network is disclosed which provides for at least one mode to control the state of a response flag and when the target device is unable to respond to an initiator device request.
6779047 Serial communication port arbitration between a hotsync manager and a wireless connection manager  
Within one embodiment of the present invention, arbitration software operating on a computer is able to determine whether communication software utilizes the same serial communication (COM) port...
6775282 Bus communication  
An apparatus includes at least two circuits having interfaces, for transmitting and receiving bus formatted messages and a port coupled to receive messages from the interfaces. The port broadcasts...
6769035 Same single board computer system operable as a system master and a bus target  
A same single board computer system that is operable as a system master and a bus target and methods of operating the same are described. In one system, a processor having a system master mode of...
6766405 Accelerated error detection in a bus bridge circuit  
A split operation such as a split read or a split write is handled by a bus bridge circuit. The bus bridge receives the read or write command from a requesting device, where the command includes a...
6763415 Speculative bus arbitrator and method of operation  
A bus interface unit for transferring data between a plurality of bus devices. The bus interface unit comprises: 1) a destination prediction circuit for predicting a predicted destination bus...
6763413 Method for the serial transfer of data between two electronic bus stations and bus station for use in said method  
A bus protocol for serial transfer of data between two electronic components via a 3 line bus connection. The bus protocol according to the invention transfers data words without handshake signals...
6760797 Method for allocating channel in device having digital interface  
A method for allocating a channel in a digital device having a digital interface such as the IEEE1394. The method for allocating a channel to a specific output plug of a digital device having a...
6757766 Bus system for a highly scalable multiprocessor system and method for transmitting information in the bus system  
The invention relates to a bus for a highly scalable multiprocessor system, to a redundant bus system that utilizes this bus, and to a method for transmitting information in this bus system. To...
6757767 Method for acceleration of storage devices by returning slightly early write status  
The present invention features a method for improving data flow from a host initiator on a first data bus to a target tape storage device on a second data bus, both buses being connected to one...
6754747 System and method for configuring an I/O bus  
A system and method are provided for configuring an I/O bus. The system and method includes a plurality of adapter cards. A plurality of adapter card slots associated with the I/O busses receive...
6754749 Multiple use integrated circuit for embedded systems  
An integrated circuit includes a microcontroller core interconnected with a peripheral component interconnect (PCI) interface configurable as a PCI host/CPU bridge when the integrated circuit is...
6754692 Configurable power distribution circuit  
Briefly, in accordance with one embodiment of the invention, a circuit includes: a physical arrangement of power transistors. The circuit is adapted to couple a node to a power bus segment. The...
6751697 Method and system for a multi-phase net refresh on a bus bridge interconnect  
A method and system for a multi-phase net refresh on a bus bridge interconnect, the interconnect comprising a number of nodes, a bus bridge, and a number of buses, are described. In one...
6748505 Efficient system bus architecture for memory and register transfers  
A method of efficiently performing transactions on the system bus which includes at least a request signal line, a grant signal line, a set of address signal lines, and a set of data signal lines...
6748464 Semiconductor device comprising CPU and peripheral circuit wherein control unit performs wait cycle control that makes peripheral circuit wait a predetermined time before responding to CPU  
A semiconductor device includes a CPU and many peripheral circuits that are accessed by the CPU. Each peripheral circuit includes a wait control register which changeably holds wait cycle number...
6745261 Method for connecting caches in external storage subsystem  
A plurality of independent cache units and nonvolatile memory units are provided in a disk controller located between a host (central processing unit) and a magnetic disk drive. A plurality of...
6745271 Fast data transfer system with multiple memory modules and controller  
Memory modules and a controller are arranged and two clock lines are provided to go and return along the arrangement of the memory modules and the controller. A first basic clock and a second...
6745258 Raid system having multiple reply queues for use with multiprocessor host  
An SMP computing system has a RAID controller and an interconnect bus system for communication processors and the RAID controller. There are in host memory a plurality of reply queues, at least...
6745272 System and method of increasing bandwidth for issuing ordered transactions into a distributed communication system  
A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into...
6742071 Real-time I/O processor used to implement bus interface protocols  
A circuit that may be configured to store data and interface with an external device. The circuit may provide one or more control signals to the external device.
6742052 Wireless system bus  
A mobile or desktop computer having a system bus that is exposed externally using a wireless transceiver so that input and output devices within proximity of the computer can be configured for...
6738836 Scalable efficient I/O port protocol  
A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of...
6738844 Implementing termination with a default signal on a bus line  
Implementing termination on a bus. According to one embodiment of the present invention a driver drives a default signal on to a line, then drives an information signal on to the line, and then...
6735713 System for suspending current bus cycle of microprocessor upon receiving external bus retry signal for executing other process and re-staring the suspended bus cycle thereafter  
The present invention is directed to a microprocessor (MPU) 10 comprising a bridge chip 12 including a bus retry output part (40) for outputting a bus retry (BRTY) signal; a bus retry detection...
6735653 Bus bandwidth consumption profiler  
A bus bandwidth consumption profiler for measuring and reporting bus cycle utilization in a system having multiple bus masters, including master counters paired with the masters to count cycles of...
6732208 Low latency system bus interface for multi-master processing environments  
A bus interface to a split transaction computing bus having separate address and data portions is provided. The bus interface contains separate address and data interfaces for initiating and...
6728890 Method and apparatus for controlling a bus clock frequency in response to a signal from a requesting component  
A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to...
6728808 Mechanism for optimizing transaction retries within a system utilizing a PCI bus architecture  
A mechanism for optimizing transaction retries within a system utilizing a peripheral component interconnect (PCI) bus architecture. Specifically, one embodiment of the present invention includes...
6725307 Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system  
A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch,...
6725306 DEBUG mode for a data bus  
A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a...
6725305 Method and apparatus for using a bus as a data storage node  
The present invention is a method and apparatus for dynamically holding valid data logic levels on a bus by taking advantage of the inherent storage capacity of the bus. The bus speed is increased...
6721831 Method for controlling bus in digital interface  
A method for controlling a bus in a digital interface is disclosed. In the present method, after a self identifying process when a bus reset occurs, a determination is made whether a node which...
6721918 Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect  
A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set...
6721832 Data processing system and bus control method for stream data transfer  
A data processing system includes a bus, a plurality of devices connected to the bus, and a unit for executing data transfer between at least two of the plurality of devices via the bus, using one...
6721813 Computer system implementing a system and method for tracking the progress of posted write transactions  
A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem...
6717834 Dual bus memory controller  
A memory controller initiates a first memory access in response to receipt of a first memory access request. The memory controller receives a second memory access request and initiates a second...
6715015 Apparatus and method for generating command and/or response frame for control of digital equipment  
The present invention relates to an apparatus and method for generating a command frame and/or a response frame transmitted and received to/from a digital equipment. The apparatus includes: a host...
6715014 Module array  
A module array includes a lead-in transmission line from a driving source. The lead-in transmission line ends with a series impedance between the lead-in transmission line and a star node. The...
6715049 Microcomputer and information processing system  
A microcomputer and an information processing system protect data stored therein and secure the safety of the data. The microcomputer (1) has a memory (3), a read protect register (13), and a...
6714128 Motor vehicle lighting system  
A motor vehicle lighting system includes a master controller, a smart light, and a hot bus. The master controller is electrically couplable to a power supply and is adapted to receive an input...
6708246 Signal processing device with bus ownership control function  
A signal processing device includes an integrated processor, a video processing unit coding a video signal, and an interface controlling a bus ownership between the integrated processor and an...
6708244 Optimized I2O messaging unit  
A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more...
6708277 Method and system for parallel bus stepping using dynamic signal grouping  
In a parallel interface bus structure (FIG. 4, 110), a determination is made as to the number of signals will be allowed to change state during a clock period. This determination is made in...
6708236 Bus control apparatus  
Bus control apparatus solves the problem that a high-speed bus which supports only burst transfer cannot be used when the boundary of a transfer memory address is not coincident with a unit...
6704830 Apparatus for wire-or bus expansion between two instrument chassis  
An expanded WIRE-OR Bus structure has a first WIRE-OR Bus arrangement and a second WIRE-OR Bus arrangement. Each of the first and second WIRE-OR Bus arrangements have connected thereto at least...
6704850 Method and apparatus for determining the width of a memory subsystem  
A method and apparatus for determining a width of an external memory is described. The method comprises reading a data from memory, and if the data matches an expected data key, determining the...
6704847 Host access to shared memory with a high priority mode  
A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of...
6701387 Adaptive data fetch prediction algorithm  
A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device...
6701398 Global bus synchronous transaction acknowledge with nonresponse detection  
An integrated multi-processor system with clusters of processors on a high speed split transaction bus uses a transaction acknowledge (TACK), by a target device in response to receiving a request...