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6898649 Arbiter for queue management system for allocating bus mastership as a percentage of total bus time  
An arbiter (7) is provided for a QMS having multiple queue users (5A to 5D), each having real time requirements for mastership of a bus (31). The arbiter (7) is arranged so that the amount of time...
6892258 Hardware semaphores for a multi-processor system within a shared memory architecture  
A circuit generally comprising a memory element and a controller. The memory element may define a semaphore allocatable to a resource. The controller may be configured to (i) present a granted...
6892259 Method and apparatus for allocating computer bus device resources to a priority requester and retrying requests from non-priority requesters  
A target device in a computer bus system allocates resources by selecting a priority requester for allocation of scarce resources. In a non-bus arbiter configuration, the first initiator device to...
6889275 Resource interconnection patterns in a customized memory organization context  
A system and method are provided that include determining optimum memory organization in an electronic device, wherein further determined are optimum resource interconnection patterns. One aspect...
6889265 Apparatus and method to allow and synchronize schedule changes in a USB enhanced host controller  
An apparatus and method for making changes to an active schedule being processed by a host controller is disclosed. The apparatus and method includes examining a transaction descriptor,...
6889276 Priority mechanism for scheduling isochronous and asynchronous transactions on a shared bus  
A plurality of asynchronous and isochronous transactions on a shared bus are scheduled such that asynchronous latency is minimized while providing a maximum latency for isochronous transactions....
6886063 Systems, devices, structures, and methods to share resources among entities  
Systems, devices, structures, and methods are provided to allow resources to be shared among a plurality of processors. An exemplary system includes a mechanism to grant exclusive control of a...
6883042 Method and structure for automatic SCSI command delivery using the packetized SCSI protocol  
A SCSI initiator system includes a Packetized SCSI Protocol hardware packet engine that automatically transmits Packetized SCSI protocol command blocks to a SCSI target with substantially zero...
6879602 Synchronizing method and bridge  
An offset value corresponding to the difference between counter values of cycle time counters in two buses is obtained and stored, so that the buses are connected, the value of a first cycle time...
6880027 System and method of evaluating universal serial bus function  
The present invention provides a universal serial bus function evaluator connected between a computer and an universal serial bus function. The universal serial bus function evaluator comprises: a...
6877067 Shared cache memory replacement control method and apparatus  
In a multiprocessor system in which a plurality of processors share an n-way set-associative cache memory, a plurality of ways of the cache memory are divided into groups, one group for each...
6877052 System and method for improved half-duplex bus performance  
A method for dynamic preemption of read returns over a half-duplex bus during heavy loading conditions involves asserting a preempt signal by a first agent to indicate that the first agent has a...
6874050 Circuit and method for expanding a serial bus  
A serial bus expansion circuit, system, and method are provided. In one embodiment, the serial bus expansion circuit comprises a bus distribution circuit selectively coupling a serial bus to one...
6873948 Method and apparatus for emulating a device within a data processing system  
A method and apparatus in a data processing system for mimicking a device attached to a bus. Signaling is detected on the bus indicating a request to access the device. The bus is then monitored...
6868464 Method, apparatus, and system for multi-line communication  
According to one aspect of the invention, a method is provided in which one or more requests are received to transmit data between a first device and a second device via a bus having a plurality...
6865634 Method and apparatus for deadlock prevention in a distributed shared memory system  
A distributed shared memory system having a memory access request transaction queue having a plurality of queue slots prevents occurrences of deadlocks. The distributed shared memory system is...
6857029 Scalable on-chip bus performance monitoring synchronization mechanism and method of use  
A bus performance monitoring mechanism for systems on a chip (SOC) is disclosed. The system comprises a muxing logic adapted to be coupled to a plurality of master devices, a plurality of slave...
6857035 Methods and apparatus for bus mastering and arbitration  
Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system....
6851005 Apparatus and method for implementing raid devices in a cluster computer system  
Apparatus and methods are provided for efficiently implementing logical-device reservations in a cluster computer system. The apparatus includes cooperating controllers programmed in firmware...
6851056 Control function employing a requesting master id and a data address to qualify data access within an integrated system  
An access control function for an integrated system is provided which determines data access based on the master id of a requesting master within the system and the address of the data. The access...
6851004 Adaptive retry mechanism  
An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency...
6848003 Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response  
A data processing system includes a plurality of nodes, which each contain at least one agent and each have an associated node identifier, and memory distributed among the plurality of nodes. The...
6845416 System and method for interfacing a CAN device and a peripheral device  
A system for interfacing a host computer to a Controller Area Network (CAN) bus. The system comprises a memory, an embedded processor and interface logic. The memory stores program code. The...
6845418 Bus system for master-slave device accesses, has multiple pseudo-delayer connected to controllers which delay and output access commands to slave devices for having longer latency periods  
A bus system and a command delivering method includes (a) delivering a first command to a first slave device, and (b) delivering a second command to a second slave device at a point in time which...
6839783 Programmable state machine interface  
A state machine interface that can be used with digital devices whose interface characteristics are not known in advance. This interface is completely programmable on a clock-by-clock basis. The...
6829659 Method, system and program product for logically disconnecting in fibre channel communication without closing the exchange  
The present invention provides fiber channel networks the ability to logically disconnect without closing an exchange pair wherein the control unit signals the channel that the channel can elect...
6829665 Next snoop predictor in a host controller  
A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which...
6826640 Bus bandwidth control system  
A system includes a central processing unit (CPU), one or more input/output (I/O) ports designed to connect with external devices, a data bus connecting the CPU with the I/O ports, bus request and...
6823410 Split transaction bus system  
To advance a read response in a split transaction bus system. An access time prediction circuit 5 measures an elapsed time from a time when a read command is issued, and outputs a parking...
6823409 Coherency control module for maintaining cache coherency in a multi-processor-bus system  
A mechanism for efficiently filtering snoop requests in a multi-processor bus system. Specifically, a snoop filter is provided to filter unnecessary snoops in a multi-bus system.
6823412 System and method for arbitration of a plurality of processing modules  
Method and apparatus for an arbitrated high speed control data bus system providing high speed communications between microprocessor modules in a complex digital processing environment. The system...
6820141 System and method of determining the source of a codec  
A system and method to determine a port that a codec is attached is disclosed. An access will be attempted to a codec, and the internal hardware of the host will watch which input port the...
6820158 Method and apparatus for a configuration ring  
A method and apparatus for a configuration ring is described. The method and apparatus include a configuration ring including a master, a first target, and a second target, the master coupled to...
6816939 Apparatus for supporting I2C bus masters on a secondary side of an I2C multiplexor  
An apparatus for supporting I2C bus masters on a secondary side of an I2C mulitplexor is disclosed. An electronic system includes a primary serial bus, multiple secondary serial buses, an...
6816934 Computer system with registered peripheral component interconnect device for processing extended commands and attributes according to a registered peripheral component interconnect protocol  
A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a...
6816809 Hardware based utilization metering  
A hardware based utilization metering device, and a corresponding method are used in a computer system having one or more central processor units (CPUs) to provide a measure of CPU utilization....
6816924 System and method for tracing ATM cells and deriving trigger signals  
A trace and debug support unit (120) that works in conjunction with a bus sniffer (112). The trace and debug support unit (120) maintains in memory one or more configurable filter rules which are...
6813664 System transmitting data in equidistance cycles using successive synchronization signals for detecting and signaling access violations  
A user terminal (1) having a communications processor (10) that carries out a cyclic data transmission. During a cyclic part (ZYK,x) of a cycle (Z,x) in which user data are transmitted, a DP...
6813767 Prioritizing transaction requests with a delayed transaction reservation buffer  
In one embodiment of the invention, a transaction queue stores a transaction request and issues a stream transaction for the stored transaction request when a slot in a set of active stream...
6810432 Method for guaranteeing a device minimun bandwidth on a usb bus  
A method of guaranteeing a minimum sustained data transfer rate to a chosen device connected to a USB bus. A set of filter drivers are inserted in the driver stacks for at least two USB devices....
6810453 Information transmitting apparatus and method, information receiving apparatus and method, and information transmitting/receiving apparatus and method  
An information transmitting apparatus is included in a system for transmitting information through a bus (B), for transmitting the information onto the bus. The information transmitting apparatus...
6807592 Quad pumped bus architecture and protocol  
A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple...
6804736 Bus access arbitration based on workload  
A computer system with a bus arbitration system adaptively assigns priority to devices on the bus based upon workload. A bus arbiter receives request signals from bus devices that require bus...
6801971 Method and system for shared bus access  
An apparatus for controlling access to a PCI bus includes a plurality of USB host controllers, each capable of being connected to a respective USB port. A plurality of PCI cores are each coupled...
6801970 Priority transaction support on the PCI-X bus  
Support for indicating and controlling transaction priority on a PCI-X bus. Embodiments of the invention provide indicia that can be set to communicate to PCI-X-to-PCI-X bridges and Completer that...
6801961 Method for solving intermission of streaming data and associated device thereof  
A method for solving intermission of streaming data. A digital controller is used to transmit streaming data stored in a storage unit. The digital controller includes a base recording unit and a...
6801972 Interface shutdown mode for a data bus slave  
A slave device receives commands from a master device for execution on a first-in, first-out basis. A status register is responsive to a queue of commands to provide a COMMAND_STATUS_FULL signal...
6801834 Data library system having movable robotic librarian operable for accessing statically mounted drives  
An automated data library system includes a data library housing drive clusters. The drive clusters include drive arrays of disk drives. The drive clusters are statically mounted within the data...
6799233 Generalized I2C slave transmitter/receiver state machine  
A robust state machine is provided for controlling a slave interface to an I2C-bus. The state machine is configured to enforce the slave-device-protocol of the I2C specification, and to provide...
6789155 System and method for controlling multi-bank embedded DRAM  
In a computer or microprocessor-based system having a plurality of resources making memory requests of a plurality of banks of memory, a switch-based interconnect system allows multiple...