Match Document Document Title
7002928 IEEE 1394-based protocol repeater  
Systems and methods consistent with the present invention connect a remote device to a IEEE 1394-based network through an intervening telephone line, thereby enabling the remote device to...
7002984 Method and apparatus for parallel operation in a multiple access network  
A system is disclosed that improves quality-of-service (QoS) by parallel operation in a multiple access network and offers a flexible way to adjust network performance by dynamically allocating...
7003637 Disk array device with utilization of a dual-bus architecture dependent on data length of cache access requests  
In a disk control device arranged to include a CPU, a plurality of channel control units, a plurality of disk control units, a cache memory, and a data transfer integrated circuit communicably...
7000131 Apparatus and method for assuming mastership of a bus  
The present invention is generally directed to an apparatus and method for reducing excess power consumption of a bus master circuit component for use in a multi-bus master system. In one...
6996647 Token swapping for hot spot management  
A method and apparatus are provided for efficiently managing hot spots in a resource managed computer system. The system utilizes a controller, a series of requestor groups, and a series of loan...
6996645 Method and apparatus for spawning multiple requests from a single entry of a queue  
Coded requests are received from Memory Port Interfaces (608 and 612) and stored into Outgoing Queue (604). Coded requests are also received from Transaction Pipeline (610), some of which may be...
6996644 Apparatus and methods for initializing integrated circuit addresses  
Multiple ICs communicate with a controller through a shared bus. The ICs are also joined to an output of the controller in a daisy chain configuration. Each IC includes an input for receiving a...
6993611 Enhanced general input/output architecture and related methods for establishing virtual channels therein  
A point-to-point interconnection and communication architecture, protocol and related methods. System resources are dynamically shared based on contents of information received for transmission...
6990539 Apparatus and method of implementing BREQ routing to allow functionality with 2 way or 4 way processors  
An apparatus for implementing bus request routing to allow functionality with 2 way or 4 way processors, includes a bus configured to provide bus request routing; and a bus request route switching...
6990537 System and method for controlling multi-component communications via a bus by causing components to enter and exit a high-impedance state  
A method for controlling communication on a bus connecting a first processor, a second processor, and a device. The method transmits a first control signal from the first processor to the second...
6985979 Digital data processing device, bus controlling method, bus controlling program and recording medium  
It is an object to restore states of isochronous resources and logic plugs to normal states when failures occur in release of the isochronous resources and disconnection of the logic plugs....
6985980 Diagnostic scheme for programmable logic in a system on a chip  
A scheme for freezing the clock of a CSOC to obtain a static view of the hardware for debugging purposes. A breakpoint unit is programmed to break on specific conditions or sequence of events. The...
6981034 Decentralized management architecture for a modular communication system  
A decentralized management model enables a plurality of interconnected modules to be managed and controlled as an integrated unit without requiring any one of the interconnected modules to operate...
6978391 Asynchronous bus interface circuit, method of controlling the circuit, microcomputer, and device controlling method  
In microcomputers for being embedded into various devices, asynchronous bus interface circuits are arranged between an asynchronous bus and macro circuits, operating in synchronization with an...
6978328 Bus system, memory system, printed circuit board and directional coupler  
A bus system for carrying out data transfer between one bus master and a plurality of bus slaves. The bus system includes plural directional couplers which are formed by arranging respective parts...
6978329 Programmable array-based bus arbiter  
A bus arbiter for arbitrating bus access requests from N bus requestor devices. The bus arbiter comprises N one-hot registers, each one-hot register associated with a corresponding bus requester...
6976106 Method and apparatus for speculative response arbitration to improve system latency  
A method and apparatus for speculative response arbitration to improve system latency have been described.
6973526 Method and apparatus to permit external access to internal configuration registers  
Access to internal configuration registers on a computer system's chipset using an external micro-controller is provided. A SMB configuration read command including a register address may be...
6973607 Method and apparatus for testing electronic components  
An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the...
6973520 System and method for providing improved bus utilization via target directed completion  
An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate...
6968406 System and method for arbitrating access between common access requests on a bus  
A system and method of arbitrating access on a bus includes a bus, a bus expander, a boot module, and a management module. The bus expander includes an access engine, a first bus interface, a...
6963941 High speed bus topology for expandable systems  
A high-speed short-loop bus topology that routes the bus into a first expansion connector and out of a first expansion card inserted within the connector is disclosed. The bus is not routed out of...
6963968 Signal transmission device and method  
A signal transmission device and method wherein the signal transmission device includes a first communication part for transmitting a signal through a number of high-speed serial buses, and a...
6963940 Measuring utilization of individual components of channels  
The utilization of various individual components of a channel is determined in order to learn which portion of a channel is busy and to what extent that portion is busy. The determination of a...
6961313 Arrangement for verifying randomness of TBEB algorithm in a media access controller  
A testing arrangement is configured for evaluating the randomness of a number generated by a network device under test configured for sending a data packet on a network medium and generating a...
6959350 Configurable USB interface with virtual register architecture  
An interface controller includes configuration circuitry generated based on a configuration package associated with endpoint configuration parameters. The configuration circuitry is used for...
6954810 Transparent switch  
A transparent switch is able to emulate the arbitration and addressing steps for devices that are normally connected to a bus-type communications network. The switch is connected to the devices in...
6954809 Apparatus and method for accessing computer system resources via serial bus  
An apparatus for monitoring the state of computer system resources. According to the invention, the apparatus includes bus interface logic and a queue. The bus interface logic is used to interface...
6954209 Computer CPU and memory to accelerated graphics port bridge having a plurality of physical buses with a single logical bus number  
A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality of Accelerated Graphics Port (AGP) buses. Each of the plurality of AGP buses...
6952750 Method and device for providing a low power embedded system bus architecture  
The tristateless bus interface communication scheme according to the present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present...
6948017 Method and apparatus having dynamically scalable clock domains for selectively interconnecting subsystems on a synchronous bus  
In one form, a method for communicating among subsystems coupled to a bus of a computer system on an integrated circuitry chip includes operating subsystems at independent clock frequencies when...
6948019 Apparatus for arbitrating non-queued split master devices on a data bus  
A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An...
6944696 Data processing processor  
A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use...
6944695 Method and apparatus for connecting devices to a bus  
A two-wire serial (TWS) bus allows bus mastering by any device on the bus utilizing pull-ups. The bus is actively driven low, but typically pulled high by pull-up resistors for each device on the...
6941390 DMA device configured to configure DMA resources as multiple virtual DMA channels for use by I/O resources  
Various embodiments of a system and method for configuring a set of DMA resources as multiple virtual DMA channels are disclosed. In one embodiment, a system may include a context memory...
6937599 Data source, data conversion device, inverse data conversion device, auxiliary data file generation device, reception method, medium and information aggregate  
A data source has a data converting part for converting inputted data to predetermined data packets. A data buffer stores the data packets. A descriptor list stores a descriptor to which...
6938112 Use of bus hold to prevent bus contention between high speed processor and slow peripheral  
The present invention discloses a method and apparatus for preventing contention on a common data bus between a CPU and a peripheral device with which the CPU exchanges data. A transceiver with...
6934789 Interface, structure and method for transmitting data of PCI bus which uses bus request signal for judging whether a device supporting dual transmission mode  
A bus data interface, structure and method for transmitting the data of a PCI bus is disclosed. The bus data interface comprises a high-bit transmitting buffer, a low-bit transmitting buffer, a...
6931467 Memory integrated circuit device which samples data upon detection of a strobe signal  
A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications...
6931464 Method for connecting gigabit interface converters with serial identification capability into an active two-wire serial bus  
A method for connecting an interface to a serial bus is provided comprising the steps of sensing at least one identification line for the interface, identifying an interface type from the at least...
6931470 Dual access serial peripheral interface  
A dual access peripheral interface uses a shared data bus (16) for communication with dual master units (30,32) coupled to a common peripheral device (34). Each master control unit provides a...
6928499 Microcomputer used in system having external storing unit and/or peripheral unit  
An external area judging unit judges according to an address signal of a CPU whether the access to an external memory or the access to a peripheral unit is desired. In cases where the access to...
6925516 System and method for providing an improved common control bus for use in on-line insertion of line replaceable units in wireless and wireline access systems  
There is disclosed a system and method for providing an improved common control bus for use in the on-line insertion of line replaceable units (such as circuit board cards) into a backplane of a...
6922735 Management of co-processor information by integrating non-program information with program information  
A system including a host processor (11) operating in combination with one or more co-processors (13) is disclosed. In this system, a file storage facility (17) stores executable files (40) that...
6917996 Bus control system and method of controlling bus  
An external bus control device 2 has first and second bus controllers 15, 16 and an external bus arbiter 17. The bus controllers 15, 16 correspond to devices (for example, SRAM, DRAM) connected to...
6915396 Fast priority determination circuit with rotating priority  
The invention describes a system for and a method of creating and using dependencies to determine the order of servicing transaction requests in a multiple queue environment. When more than one...
6912609 Four-phase handshake arbitration  
A four-phase arbitration system employs a master and a slave arbiter. The master arbiter operates to provide ownership of a bus to a first device if a second device, coupled to the slave arbiter...
6904480 Testing a bus using bus specific instructions  
A system for generating transactions on a bus includes at least one instruction memory storing predefined bus stimuli instructions and at least one phase generator coupled between the bus and the...
6904481 Bus sequence operation with automatic linking from current I/O information to subsequent I/O information  
In a computer system, a bus adapter processes bus operation information structures for performing bus operations by automatically starting processing each bus operation information structure after...
6898678 Shared memory with programmable size  
A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of...