|
Match
|
Document |
Document Title |
|
|
7206960 |
Bus clock frequency management based on device load
A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and...
|
|
|
7206874 |
Status display-enabled connector for a universal asynchronous receiver/transmitter
A Universal Asynchronous Receiver/Transmitter (UART) connector capable of displaying status includes a capturing unit, a driving unit and a display unit. The UART connector captures asynchronous...
|
|
|
7206946 |
Disk drive system for starting destaging of unwritten cache memory data to disk drive upon detection of DC voltage level falling below predetermined value
A disk array system including at least one channel control portion, at least one disk control portion, a cache memory, a cache switch, a shared memory, a power unit, and a casing for storing the...
|
|
|
7206881 |
Arrangement and method for controlling dataflow on a data bus
The present invention relates to a method and arrangement for controlling dataflow on a databus, especially for avoiding reception problems by a receiver unit. The databus connects at least one...
|
|
|
7203788 |
USB-to-VGA converter
A USB-to-VGA converter includes a USB controller connectable to a USB port of a computer for receiving USB based display signals from the computer, a VGA controller connectable to a display device...
|
|
|
7203787 |
Information processing apparatus and method that utilizes stored information about a mountable device
An IEEE 1394-compliant communication bus connects a printer and host computer so as to allow communication. The configuration ROM of the printer stores information about devices mountable on the...
|
|
|
7200685 |
Communication apparatus for communicating data between separate toplogies, and related method, storage medium, and program
In a connection form of PC-printer-digital camera, for example, to enable a printing function from a PC to a printer, a direct printing function from a digital camera to a printer, and a function...
|
|
|
7200704 |
Virtualization of an I/O adapter port using enablement and activation functions
A method for configuring a communication port of a communications interface of an information handling system into a plurality of virtual ports. A first command is issued to obtain information...
|
|
|
7197577 |
Autonomic input/output scheduler selector
The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped...
|
|
|
7197590 |
Method and apparatus for connecting LPC bus and serial flash memory
A method and apparatus for connecting low pin count (LPC, hereinafter) bus and serial flash memory is provided for converting the interface between a LPC bus and a serial flash memory in personal...
|
|
|
7191276 |
Hub chip for one or more memory modules
One embodiment of the invention provides a hub chip comprising: an address bus input for receiving a plurality of successively sent portions of address and/or command data, a shift register which...
|
|
|
7187265 |
Equipment housing with interfacing computer
An equipment housing is provided upon which heavy computing equipment, such as servers, routers, switches, and others may be mounted. A computing device is attached to the housing. The computing...
|
|
|
7188200 |
Method for data exchange between an operating and monitoring program and a field device
In connection with a method for the data exchange between an operating and monitoring program BA and a field device, which is connected via a field bus adapter with the internet, the operating and...
|
|
|
7185127 |
Method and an apparatus to efficiently handle read completions that satisfy a read request
A method and an apparatus to efficiently handle read completions that satisfy a read request are presented. The apparatus comprises a first port to receive data that partially satisfies a read...
|
|
|
7185213 |
Method for PCI Express power management using a PCI PM mechanism in a computer system
A method for PCI ExpressPower Management using a PCI PM mechanism in a computer system. The computer system includes a PCI PME (Power Management Event) controller and a PCI Express Root Complex....
|
|
|
7185341 |
System and method for sharing PCI bus devices
A plurality of processors share a device using a common PCI bus. Each processor includes a PCI addressable memory area where data sent to or received from the device is stored. Each processor...
|
|
|
7185143 |
SAN/NAS integrated storage system
In a storage system directly connected to a network, if conventional interfaces and protocols are used when an I/O command issued from a file server is transmitted to the storage system, the...
|
|
|
7181562 |
Wired endian method and apparatus for performing the same
A method and associated apparatus is provided for operating an electronic device in accordance with a wired endian format. More specifically, the wired endian format requires multi-byte values be...
|
|
|
7180911 |
System and method for communicating data packets
A method for communicating data packets is provided that includes receiving a data packet at a first processor. A packet handle and interface handle are attached to the data packet. The packet...
|
|
|
7174402 |
Systems, network devices and methods for highly configurable peer-to-peer communications between network devices communicating via a common bus
A system and method are provided for initiating peer-to-peer communications via a network bus. The system includes a bus controller in electrical communication with the network bus for controlling...
|
|
|
7170815 |
Memory apparatus having multi-port architecture for supporting multi processor
A memory apparatus for supporting a multiprocessor function enables data of different characteristics to be stored in one memory, thereby reducing the area of on the system board and decreasing...
|
|
|
7171445 |
Fixed snoop response time for source-clocked multiprocessor busses
An interfacing logic is implemented in one or more processors and a memory controller in a multiprocessor system. The interfacing logic enables all processors to receive snoops and snoop responses...
|
|
|
7171505 |
Universal network interface connection
An interface connection is described for joining a host device, such as a Network Processor, to peripherals such as modems, printers, local area networks, Ethernets and Token-Ring interfaces. The...
|
|
|
7165132 |
Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged
In one embodiment, a processing node includes a plurality of processor cores and a reconfigurable interconnect. The processing node also includes a controller configured to schedule transactions...
|
|
|
7165131 |
Separating transactions into different virtual channels
In one embodiment of the present invention, a method may include separating incoming transactions to an agent of a coherent system into at least a first channel, a second channel, and a third...
|
|
|
7165005 |
Measurement module interface protocol database and registration system
System and method for providing a measurement module (MM) interface for configuring a measurement system. The method includes creating a MM and one or more MM interface programs implementing...
|
|
|
7165133 |
Multiprocessor system having shared buses, prioritized arbitration, and clock synchronization circuitry
A multiprocessor system having a plurality of processor elements each of which obtains right to use bus of a first or second shared bus in response to a transfer request for control system data or...
|
|
|
7162258 |
Light fixture wireless access points
An access point for a wireless local area data communications network is designed to derive power from a lighting fixture. In one arrangement, the access point includes a housing configured to be...
|
|
|
7159061 |
Link layer device with configurable address pin allocation
Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device...
|
|
|
7159047 |
Network with programmable interconnect nodes adapted to large integrated circuits
A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first...
|
|
|
7159065 |
Method for issuing vendor specific requests for accessing ASIC configuration and descriptor memory while still using a mass storage class driver
A bridge-chip may interface a Universal Serial Bus to a mass storage device. Communications of the universal serial bus may be examined to determine a command block wrapper (CBW) of a bulk...
|
|
|
7155546 |
Multiple physical interfaces in a slot of a storage enclosure to support different storage interconnect architectures
Provided is a system for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the...
|
|
|
7155554 |
Methods and apparatuses for generating a single request for block transactions over a communication fabric
Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communications fabric. A first functional block...
|
|
|
7152133 |
Expanded functionality protocol adapter for in-vehicle networks
The invention is an improved protocol adapter for in-vehicle networks for diagnostics, analysis and monitoring. The invention has a pass through feature (voltage translator)/smart mode that allows...
|
|
|
7148723 |
Common controller area network interface
An electronic interface is provided for connecting to various types of networks. The network places a data stream on a bus high signal and a bus low signal. The interface includes a ground...
|
|
|
7149827 |
Methods and apparatus for tristate line sharing
Methods and apparatus are provided for interconnecting on-chip components, such as components on a programmable chip, with off-chip components through a variety of buses, fabrics, and input/output...
|
|
|
7149913 |
Bus clock frequency management based on characteristics of an application program
A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and...
|
|
|
7146519 |
Bus clock frequency management based on device bandwidth characteristics
A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and...
|
|
|
7145915 |
Circuit and method for exchanging signals between network nodes
In a network node attached to a serial bus, a first count value is incremented beginning with the start timing of a child notify signal transmitted from the node to the bus until the end timing of...
|
|
|
7146441 |
SRAM bus architecture and interconnect to an FPGA
An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of...
|
|
|
7146442 |
Motherboard having a non-volatile memory which is reprogrammable through a video display port
A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video...
|
|
|
7139852 |
Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method...
|
|
|
7136907 |
Method and system for informing an operating system in a system area network when a new device is connected
A method and system are provided for dynamically informing an operating system (OS) of a distributed computer system, when a (new) device is added on the network. An OS registers with the subnet...
|
|
|
7136947 |
System and method for automatically synthesizing interfaces between incompatible protocols
A system and method for enabling Intellectual Property (IP) Blocks to be reused at a system level. The present invention represents the IP blocks as blocks that exchange messages without needing to...
|
|
|
7136946 |
Packet-based switch for controlling target computers
A method and system for converting the output of a communications port (e.g., a serial port or a USB port) into video signals representing the output of a terminal using a KVM switch. Upon...
|
|
|
7132927 |
Universal serial bus extension cable
A controller capable of being located in a peripheral device or host, is capable of engaging in data communications with a host or peripheral device over a power line. A power line interface...
|
|
|
7133944 |
Media access controller with power-save mode
There is provided a media access controller with a power-save mode. Particularly, the media access controller of the present invention minimizes power loss by disabling clocks applied to all...
|
|
|
7133953 |
Data transmission device used to forward data received at a first device for a second device to the second device
A data transmission device is used to forward data that have been received from a first device, and are intended for a second device, to the second device. The data transmission device described...
|
|
|
7129746 |
System-on-a-chip integrated circuit including dual-function analog and digital inputs
An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to...
|
|
|
7127544 |
Data transfer apparatus and data transfer method
A data transfer apparatus for transferring data between a system bus and a local bus at a high speed is provided. A bus bridge 101 is connected between a system bus 132 and a local bus 137. ...
|