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6889265 Apparatus and method to allow and synchronize schedule changes in a USB enhanced host controller  
An apparatus and method for making changes to an active schedule being processed by a host controller is disclosed. The apparatus and method includes examining a transaction descriptor,...
6886050 Method for controlling a communication terminal device and rewritable storage medium having initialization setting data  
A communication terminal device autonomously activates a specific function predetermined by a host device even when the communication terminal device is off-line when the power turns on. The...
6883050 Optimized POD module/host interface  
An interface between a point of deployment (POD) module and a host device, such as a set-top terminal for cable television selectively integrates the POD module and the host such that th POD...
6879602 Synchronizing method and bridge  
An offset value corresponding to the difference between counter values of cycle time counters in two buses is obtained and stored, so that the buses are connected, the value of a first cycle time...
6880026 Method and apparatus for implementing chip-to-chip interconnect bus initialization  
A method and apparatus are provided for implementing chip-to-chip interconnect bus initialization. The chip-to-chip interconnect bus includes first and second unidirectional buses for full duplex...
6880027 System and method of evaluating universal serial bus function  
The present invention provides a universal serial bus function evaluator connected between a computer and an universal serial bus function. The universal serial bus function evaluator comprises: a...
6877050 Data transfer device and method thereof  
When data is transferred from a controller of a liquid crystal display device to each driver through a predetermined number of signal lines, the Transferring Data are divided into a plurality of...
6877051 Consistency checking mechanism for configuration parameters in embedded systems  
An arrangement is provided for consistent parameter configuration in an embedded system. A consistent parameter configuration mechanism comprises a management client and a configuration manager....
6877067 Shared cache memory replacement control method and apparatus  
In a multiprocessor system in which a plurality of processors share an n-way set-associative cache memory, a plurality of ways of the cache memory are divided into groups, one group for each...
6874047 System and method for implementing an SMBus/I2C interface on a network interface card  
A system and method for implementing an SMBus/I2C interface in a computer connectable to a network. The system includes a plurality of devices communicably coupled to an SMBus. The system operates...
6870855 Data communication method, electronic apparatus, and physical-layer-control integrated circuit  
In the 1394 communication, communication at a data rate of S100, S200, S400, S800, S1600, S3200 or at a faster speed in the future can be performed. When the 1394 communication is performed with...
6871247 Mechanism for supporting self-modifying code in a harvard architecture digital signal processor and method of operation thereof  
For use in a processor having separate instruction and data buses, separate instruction and data memories and separate instruction and data units, a mechanism for, and method of, supporting...
6868463 Audio data recording apparatus and audio data sending/receiving method of the apparatus  
The apparatus and method for transferring audio data to a data recorder adopting a personal computer bus to receive audio data enters into data communication mode over a bus without conducting...
6868464 Method, apparatus, and system for multi-line communication  
According to one aspect of the invention, a method is provided in which one or more requests are received to transmit data between a first device and a second device via a bus having a plurality...
6862649 Behavioral translation of datalink messages between different protocols and platforms  
The digital communication system (DCS) provides communication between users utilizing digital communication protocols. The DCS includes a first protocol interface system in communication with a...
6859068 Self-correcting I/O interface driver scheme for memory interface  
A self-correcting I/O interface driver scheme uses a delay difference detector to detect a difference in delays between an I/O data path and an I/O clock path. The delay difference detector inputs...
6854028 Disk drive control for improving the operation of a computer subjected to motion  
An apparatus, method and program product are operable for controlling the operation of a disk drive in a computer subjected to motion, and comprise monitoring the motion of the computer and...
6850956 Method and apparatus for obtaining and storing data during automated data processing  
A number of items of data from a data source (12) can be processed and then supplied to a data destination (16, 17). The data may include image data, text data, numeric data or other types of...
6847617 Systems for interchip communication  
In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to...
6847975 Proxy processing method  
A proxy processing method to flexibly add/modify customized operations, such as customized user authentication and accounting, is provided. A state transition engine stores state information and...
6839795 Priority cross-bar decoder  
A matrix of routing cells forming a cross-bar decoder (70). Signal triplets (84, 86, 88) coupled to the cross-bar decoder (70) are assigned a priority. A register (50) provide outputs to the...
6834317 Network topology for food service equipment items  
A network topology for communication within and between food service equipment items generally comprises one or more food service equipment items, each having a controller and at least one...
6832325 Device on a source synchronous bus sending data in quadrature phase relationship and receiving data in phase with the bus clock signal  
A device on a source synchronous data bus includes a clock generation circuit which generates transmit and receive clock signals for transmitting and receiving data. The device sends data in...
6832343 Apparatus for controlling safety-critical processes  
The present invention relates to an apparatus for controlling safety-critical processes. The apparatus includes at least one safe control unit for controlling the safety-critical processes and at...
6832277 Method and apparatus for transmitting data that utilizes delay elements to reduce capacitive coupling  
A method of broadcasting N, an even integer, bits of data onto a bus that includes a first plurality of electrical conductors and a second plurality of electrical conductors. The method includes:...
6831831 Disc storage subsystem having improved reliability  
A disc storage subsystem includes a housing, at least one disc drive assembly received in a front portion of the housing, first and second controllers, and an intermediate electronic component....
6829659 Method, system and program product for logically disconnecting in fibre channel communication without closing the exchange  
The present invention provides fiber channel networks the ability to logically disconnect without closing an exchange pair wherein the control unit signals the channel that the channel can elect...
6826628 PCI-PCMCIA smart card reader  
A method and apparatus is disclosed for implementing an integrated video card and smart card reader. A single processor is used to perform both video and smart card reader functions. The processor...
6823283 Measurement system including a programmable hardware element and measurement modules that convey interface information  
System and method for measurement, DAQ, and control operations. A measurement module includes measurement circuitry for performing signal conditioning and/or signal conversion, and interface...
6823408 Electronic equipment, and method for controlling state of physical layer circuit therefor  
A system is designed to avoid problems that may occur if a physical layer misunderstands the kind of signal it receives and erroneously changes its state to a suspend state. When a node B receives...
6823416 Method and apparatus for device interface  
A method for communicating between a controller and a device with double-buffered inputs comprises the steps of providing one or more communication paths for exchanging data between the controller...
6816947 System and method for memory arbitration  
A memory access arbitration scheme is provided where transactions to a Shared memory are stored in an arbitration queue. Prior to arbitration, the transactions are compared against the contents of...
6813648 Method and apparatus for post boot-up domain validation  
A method for performing domain validation testing of SCSI devices connected to a SCSI bus is provided. The method includes booting up a computer system having a SCSI device connected to the SCSI...
6813672 EMC enhancement for differential devices  
An apparatus configured to communicate through a differential bus to a device. The apparatus may be configured to disconnect and reconnect the device in response to an abnormal reset event to...
6810459 Reduced complexity computer system architecture  
An architecture for a computer system that has lower complexity than prior computer system architectures. In one embodiment the functionality that in prior computer system architectures resides in...
6809830 Method and system for enabling a printing program to communicate with a printer  
A method and system for enabling a printing program to communicate with a printer relies on a plug and play manager to detect the presence of a printer and send a notification message to the...
6803857 Remote control system  
A controller has means responsive to a continuous press of a continuously operable key to transmit, to an electronic device, a key command indicative of a type of the pressed key, and means for...
6804263 Controlling the state of a node connected to a bus during the self identification phase of bus arbitration  
A data network has a bus to which are connected a given node, a parent node and a child node; and arbitration over acquisition of the bus is performed before data is communicated between nodes....
6804734 Device and method for switching receiving/recording device in a broadcasting connection/point-to-point connection bus enviroment  
An information processing device, method thereof and a recording medium for easily switching input signals. A broadcast connection and a point-to-point connection are established between the...
6801969 Method and apparatus for data dependent, dual level output driver  
The inter-symbol interference problem is reduced by detecting a data sequence indicating when a boost is needed on a ‘short pulse’, usually the first data pulse of the opposite polarity after a...
6801054 Output buffer circuit  
An output buffer circuit is disclosed that can enhance AC performance and suppress reflected noise. An output buffer circuit can include a first driver circuit (21) and at least one second driver...
6799239 Centrally distributed serial bus  
A bus for a computer system receives serial data from each subsystem and simultaneously broadcasts the data to all subsystems. The computer system includes bus interface logic in each subsystem....
6795887 Modular MFP/printer architectures  
Modularized intra-system architectures for printer and multifunction peripheral (MFP) devices are based on disintegrating traditionally highly integrated systems into separate system components...
6795882 High speed asynchronous bus for an integrated circuit  
An apparatus for providing a high speed asynchronous bus for a plurality of modules of an integrated circuit is disclosed. Each of the modules may comprise one or more clock domains. The apparatus...
6792491 Invoking ACPI source language code from interrupt handler  
In one embodiment of the invention, an embedded controller receives an interrupt command and a query number from a system management interrupt (SMI) handler. The embedded controller generates a...
6792490 System and method for hiding peripheral devices from a host processor in a computer system  
A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at...
6792505 System apparatus and method for storage device controller-based message passing having effective data channel bandwidth and controller cache memory increase  
Controller for coupling data between a data storage system and a host includes a first processor and a first RAM coupled to the first processor; a first auxiliary processor including a first...
6789146 Socket for receiving a single-chip video controller and circuit board containing the same  
A circuit board socket is provided which is adapted to accept a plug-in single video controller having embedded video memory. The socket allows a circuit board to be easily wired to accommodate...
6785775 Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues  
A method of and apparatus for improving the scheduling efficiency of a data processing system using the facilities which maintain coherency of the system's level cache memories. These efficiencies...
6785778 Share masks and alias for directory coherency  
A directory tag for each cache line in a memory within a multiprocessor distributed memory system includes a share mask and an alias signature. The share mask is used to keep track of entities of...