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8244791 Fast carry lookahead circuits  
A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit...
7734675 System and method for generating a binary result in a data processing environment  
A method for processing data includes generating one or more binary results based on one or more inputs and receiving one or more of the binary results. One or more conditional carryout signals...
7716270 Carry-ripple adder  
A carry-ripple adder has four summing inputs for receiving four input bits having the significance w that are to be summed, three carry inputs for receiving three input carry bits having the...
7689643 N-bit constant adder/subtractor  
An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every...
7562107 Mixed-type adder comprising multiple sub-adders having different carry propagation schemes  
Disclosed is a mixed-type adder with optimized design costs. The mixed-type adder includes I sub adders, (where, I is a positive number larger than 1). An overall bit width of the mixed-type adder...
7430293 Cryptographic device employing parallel processing  
A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to...
7325024 Adder circuit with sense-amplifier multiplexer front-end  
An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and...
7159003 Method and apparatus for generating sign-digit format of sum of two numbers  
A system and method for converting two binary digits into redundant sign-digit format. The system comprises a first adder for adding the binary digits together to generate a first result. A second...
7007059 Fast pipelined adder/subtractor using increment/decrement function with reduced register utilization  
A fast pipelined adder/subtractor using increment/decrement functions with reduced register utilization. Embodiments of the present invention replace double width registers with incrementor...
6990509 Ultra low power adder with sum synchronization  
An ultra low power adder with sum synchronization which provides a power reduction method in the binary carry propagate adders by using a carry skip technique. The invention eliminates glitches at...
6970899 Calculating unit and method for subtracting  
Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing...
6965910 Calculating unit and method for adding  
A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder block, which determines whether a carry...
6959317 Method and apparatus for increasing processing performance of pipelined averaging filters  
A pipelined processor such as an averaging filter including at least one subtractor section and at least one adder section. Both of the subtractor section and the adder section have a plurality of...
6934733 Optimization of adder based circuit architecture  
An adder based circuit embodied in an integrated circuit includes an input module, a carry module and an output module. The carry module has a minimum depth defined by a recursive expansion of at...
6735612 Carry skip adder  
A carry skip adder has a plurality of ripple adders, in which at least one part of the plurality of ripple adders is divided into a plurality of groups, and a carry signal is transferred from one...
6681236 Method of performing operations with a variable arithmetic  
The process for performing operations with a variable arithmetic does not call for any shifting of the data in the different registers that come into play in the operation. The input registers can...
6584484 Incorporation of split-adder logic within a carry-skip adder without additional propagation delay  
An n-bit carry-skip adder includes a number of carry-skip stages and a logic circuit associated with one or more of the stages. The logic circuit includes split-adder logic and carry-skip logic...
6523057 High-speed digital accumulator with wide dynamic range  
A high-speed, wide dynamic range, digital accumulator includes a first adder stage in which an input addend is added to a value of a least significant part of an output of an accumulator from a...
6502120 Adder circuit employing logic gates having discrete weighted inputs and a method of operation therewith  
A circuit and method for deriving an adder output bit from adder input bits. In one embodiment, the circuit includes: (1) first, second and third threshold logic gates that generate intermediate...
6489900 Bus encoding/decoding apparatus and method  
A bus encoding/decoding apparatus and method for a low power digital signal processor (DSP), which uses a narrow data bus, is provided. The apparatus for encoding n bits of data of a data bus,...
6408320 Instruction set architecture with versatile adder carry control  
A data processing circuit has an adder unit divided into plural sections. Each section receives a subset of the bits of the operands and generates a subset of the bits of the resultant. A carry...
6263424 Execution of data dependent arithmetic instructions in multi-pipeline processors  
A single chip microprocessor has at least two parallel pipelines that each have multiple processing stages, one of which is an instruction execution stage with a full functioned arithmetic logic...
6260055 Data split parallel shifter and parallel adder/subtractor  
Shift of input data without split by a shifter, generation of code extension data by a code extension data generator, and generation of a mask signal by a mask signal generator are carried out in...
6141675 Method and apparatus for custom operations  
Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time...
6092094 Execute unit configured to selectably interpret an operand as multiple operands or as a single operand  
An execute unit including an integer operation circuit is provided. The integer operation circuit is dynamically configurable to operate upon many different widths of operands. A single pair of...
6076098 Adder for generating sum and sum plus one in parallel  
A circuit is disclosed herein which generates the sum of two numbers (A and B) and the sum plus 1 in parallel so as not to take any additional time to generate the sum plus 1 value. The circuit...
6065034 Circuit and method employing an adder for sign extending operands  
A circuit and method is provided which employs an adder for a sign extending a m bit operand. The circuit m method employs a n adder having first and second sets of n inputs and a set of n...
5995546 Digital integrator for pulse-density modulation using an adder carry or an integrator overflow  
A pulse-density modulator (10) for producing a pulse density output signal on an output line (36) representing successive parallel digital input words on input terminals (12) has a plurality of...
5959874 Method and apparatus for inserting control digits into packed data to perform packed arithmetic operations  
A processor having a circuit for performing a packed addition and/or packed subtraction operation. The decoder accesses the registers addressed by SRC1 and SRC2. These registers provide a first...
5943251 Adder which handles multiple data with different data types  
An adder circuit includes various methods to control the carry bit at data boundaries when attempting to process multiple data of multiple types. One method is to generate both propagate and...
5923579 Optimized binary adder and comparator having an implicit constant for an input  
A three-input comparator, where one of the inputs is an implicit constant, is formed with a special carry-save adder (CSA) followed by carry propagation circuitry. The special CSA uses two...
5898596 Adder which employs both carry look-ahead and carry select techniques  
The hybrid adder of the present invention uses stages of carry select functions to provide serial carries and a carry look-ahead tree structure to compute the final carries in parallel. The longer...
5883824 Parallel adding and averaging circuit and method  
An apparatus that can also be used for generating the average of two integers. The apparatus can be divided into a plurality of sub-adders that operate on sub-words of the input integers in...
RE35977 Look up table implementation of fast carry arithmetic and exclusive-or operations  
Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is...
5777918 Fast multiple operands adder/subtracter based on shifting  
A fast adder/subtracter using a decoder and shifting function instead of conventional full-adders is disclosed. The circuit is optimized for the addition of multiple operands up to 4-5 binary bits...
5726928 Arithmetic logic unit circuit with reduced propagation delays  
An improved arithmetic logic operation circuit capable of advantageously reducing propagation delay due to a logic gate for obtaining a high speed arithmetic logic unit by minimizing the number of...
5721697 Performing tree additions via multiplication  
A multiplier is modified to perform a tree addition. A first value is input to the multiplier in place of a first multiplicand. The first value is a concatenation of addends upon which the tree...
5710731 Combined adder and decoder digital circuit  
An address used to access on-chip memory is calculated by summing two binary numbers to obtain an N-bit address. The N-bit address is decoded into a one-out-of-2N signal to select the addressed...
5648925 Optimized operand formatting same  
A digital operand formatting stage that includes a first inverting means, a second inverting means having an input that is connected to the input of the first inverting means, and a third...
5548546 High-speed carry increment adding device  
A high-speed carry increment adding device having a first module including a first adder, the first adder adding a desired number of first bit inputs and generating a plurality of partitioned sums...
5497341 Sign-extension of immediate constants in an ALU using an adder in an integer logic unit  
An arithmetic-logic unit (ALU) includes a Boolean logic unit and an integer logic unit, both of which are adapted to incorporate the sign extension function for immediate constants or...
5359242 Programmable logic with carry-in/carry-out between logic blocks  
A programmable logic device. The device includes reprogrammable logic for generating at least one sum-of-products signal (113) and a control term (115). The device further includes a...
5333120 Binary two's complement arithmetic circuit  
A negation circuit (28) generates a two's complement negation by inverting only those bits of an incoming number which have a level of significance greater than the significance level at which a...
5329477 Adder circuit having carry signal initializing circuit  
Disclosed herein is an adder which comprises a Manchester-type adder circuit and which can operate as fast as a dynamic adder, and can perform addition during the clock cycle as a static dynamic...
5274581 Look up table implementation of fast carry for adders and counters  
Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is...
5239499 Logical circuit that performs multiple logical operations in each stage processing unit  
A logical circuit comprises a plurality of stage processing units, each of which includes a logical operation processing unit and a carry signal transmission controlling unit. The logical...
5229959 High order carry multiplexed adder  
A binary adder of the carry multiplex signal selection type wherein multiple levels of multiplexing between parallel carry paths is used to achieve improved adder performance as measured by adder...
5200907 Transmission gate logic design method  
A method of designing a logic circuit for implementing a predetermined boolean function defines a binary tree structure formed of transmission gate multiplexer (TGM) circuits. The TGM tree...
5189636 Dual mode combining circuitry  
A video signal processor includes cicuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit...
5189635 Digital data processing circuit  
A digital data processing circuit includes an adder circuit supplied with input data in a time-division multiplexed manner over a plurality of signal lines. The adder circuit is capable of...

Matches 1 - 50 out of 117 1 2 3 >