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7428568 Symmetric cascaded domino carry generate circuit  
A symmetric differential domino carry generate gate. In an embodiment, the load for the true inputs is equal to the load for the compliment inputs. In another embodiment, the output drive strength...
7415245 Pulse shaping signals for ultrawideband communication  
An ultrawideband radio frequency pulse is generated by shaping a carrier signal having a selected frequency with a window function. The shaped carrier is gated to produce the ultrawideband pulse....
7185042 High speed, universal polarity full adder which consumes minimal power and minimal area  
A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding...
7170317 Sum bit generation circuit  
Sum bit generation circuit includes first logic generating first signal as XOR of first and second input signals and second signal as the inverse of XOR of the first and second input signals;...
7155474 Current-mode multi-valued full adder in semiconductor device  
A full adder in a semiconductor device, includes a reference current generation unit for generating a reference current, a carry generation unit for generating a threshold current for generating a...
7039667 4-2 compressor  
A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first...
6785703 Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technology  
An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both...
6658446 Fast chainable carry look-ahead adder  
A chainable adder receives bits (A, B, C) to give complementary sum outputs (SO, SO*) and carry outputs (CO, CO*). A first stage has differential pairs (P 1 , P 2 , P 3 ) receiving bits (A, B, C),...
6567836 Multi-level carry-skip adder  
Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carry-skip paths. In one implementation, such a binary adder includes a network of...
6480875 Adder circuit and associated layout structure  
In an adder circuit, a block carry generation logic over three consecutive digits is produced from the following equations. G 0= g 2+ p 2· g 1+ p 2· p 1· g 0 / g 0=/ p 2+/ g 2·/ p 1+/ g 2·/ g...
6345286 6-to-3 carry-save adder  
A 6-to-3 carry-save binary adder is disclosed. The 6-to-3 carry-save adder includes a means for receiving six data inputs and a means for simultaneously adding the six data inputs to generate a...
6259275 Logic gate having reduced power dissipation and method of operation thereof  
A circuit for, and method of, decreasing DC power dissipation in a logic gate and a processor incorporating the circuit or the method. In one embodiment, wherein the logic gate has at least two...
6055557 Adder circuit and method therefor  
An adder (300) generates encoded outputs to conserve power. In particular, the adder provides "B2" encoded outputs which only drive one bit per every two bits at a time on conductive lines in a...
6003059 Carry select adder using two level selectors  
A carry select adder including a two level carry selector connected to multiple carry chains. Two or more adders produce at least two pairs of candidate carry-out signals in parallel. For each...
5991789 Circuit arrangement for realizing logic elements that can be represented by threshold value equations  
In a circuit arrangement wherein all logic elements can be represented in the form of a threshold value equation, for this purpose, transistors connected in parallel of a transistor unit are...
5951631 Carry lookahead adder  
A high-performance carry lookahead adder (CLA) which can reduce the delay time of the whole adder by constructing a carry generator used therein with NMOS logics, thereby effecting a high-speed...
5905667 Full adder using NMOS transistor  
A full adder includes a static logic block for generating an inverted carry with respect to multiple inputs through an inverted carry output node; a first dynamic inverter logic block for inverting...
5875124 Full adder circuit  
A full adder that operates rapidly with low power supply voltage and minimal power consumption, and further, that occupies a small area on a semiconductor element. A sum signal calculation circuit...
5818747 Small, fast CMOS 4-2 carry-save adder cell  
A CMOS 4-2 carry-save adder cell implementation. A XNOR gate is used in the computation of SUM and CARRY. By using an XNOR gate, there are no possible input permutations which will cause any output...
5761107 Method and apparatus for improving the speed of a logic circuit  
The invention is disclosed as embodied in a data processing system circuit for outputting a signal based on an evaluation of input signals coupled to the circuit. The circuit has a number of...
5596520 CMOS full adder circuit with pair of carry signal lines  
A full adder circuit has a plurality of full adders each provided for each bit. Each full adder has: a calculation block (31a) responsive to a first carry signal (C) given by a preceding stage bit...
5491653 Differential carry-save adder and multiplier  
A Carry-Save Adder circuit having differential signal response and output is provided. The circuit includes a pair of cross-coupled transistors powered by an upper voltage rail. The output of a...
5406506 Domino adder circuit having MOS transistors in the carry evaluating paths  
An improved Domino adder circuit has a carry evaluating logic, including a precharge transistor, an evaluation transistor, and three carry evaluating paths connected the precharge and evaluation...
5357456 Arithmetic circuit  
An arithmetic circuit for addition or subtraction includes a carry or borrow signal control section which includes a transfer gate having N-ch and P-ch transistors for transferring an input carry-...
5343418 Three-to-two carry save adder cell  
A three-to-two adder which takes advantage of the fact that one of the inputs lags behind the other two inputs. A gate delay is eliminated in the currently preferred embodiment, an output is...
5265044 High speed arithmetic and logic generator with reduced complexity using negative resistance  
A technique for generating a carry, AND, OR, NAND, NOR, INVERTING logic and sum and carry: operation in a one or at most two device delay by employing negative differential resistance devices....
5233233 Multiplexer for use in a full adder having different gate delays  
The semiconductor integrated circuit device includes a select gate for selectively transmitting a signal. The select gate includes a first gate for receiving and transferring a first logic signal...
5151875 MOS array multiplier cell  
A complementary metal-oxide semiconductor (CMOS) array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a...
5148387 Logic circuit and data processing apparatus using the same  
A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node....
5128892 Parallel adder  
A parallel adder has a carry between adjacent adding stages. Each of the adding stages includes a carry-generating circuit which generates a carry output signal from carry input signals to be added...
4999804 Full adder with short signal propagation path  
A full adder has a carry producing circuit responsive to at least two input bits and a low order carry bit and producing a carry bit, and a sum producing circuit responsive to the two input bits,...
4989174 Fast gate and adder for microprocessor ALU  
A fast logic gate wherein the gate output assumes a first binary state when two or more of the gate inputs assume the same predetermined binary states and wherein the gate output assumes a second...
4985862 Binary adder circuit with improved inputs  
A binary calculation circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter...
4970677 Full adder circuit with improved carry and sum logic gates  
First and second input gates and an input inverter are provided for preprocessing respectively a plurality of input signals and an additional input signal, in addition to a carry gate and a sum...
4931981 Multi-place ripple-carry adder  
A multi-place ripple-carry adder adapted for CMOS technology incorporates two types of adder cells in which the adder cells of a first type receive two operand inputs and an inverted carry input...
4920509 Binary calculation circuit  
A circuit for performing binary calculation, the circuit being of the type having at least one cell possessing: a first bit input (Ai), a second bit input (Bi), a carry-in input (Ri-1), circuitry...
4907184 Arithmetic operation circuit  
An arithmetic operation circuit is provided which includes a logic processing circuit having a first metal-oxide-semiconductor-field-effect-transistor (MOSFET) column cascade-connecting a plurality...
4905179 CMOS cell for logic operations with fast carry  
The elementary adder, as far as carry propagation is concerned, has two circuit branches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated when two operands have...
4897809 High speed adder  
An improved cascadable adder (11) which, through the use of merged logic, provides high speed operation in the presence of input loading and internal fan-out limitations. The invention may be...
4897808 Adder capable of usual addition and reverse carry addition  
An adder being adapted to switch by a control signal the respective functions of one terminal issuing a carry output and the other terminal given a signal thereto as a carry input, so that the...
4893269 Adder cell for carry-save arithmetic  
An adder cell in which the sum signal and the carry signal are formed with equal speed is provided for employment in "carry-save" adders, wherein the sum signal and the carry signal are separately...
4888723 Arrangement for bit-parallel addition of binary numbers with carry-save overflow correction  
A series of adders (AD i ) with inputs for binary number bits of the same significance, which output intermediate sum and carry words that are combined to form sum words, are provided for the...
4873659 C-MOS arithmetic - logic unit with high carry propogation speed  
The arithmetic-logic unit has elementary cells performing logic addition, one for each pair of operand bits, which are particularly optimized as far as carry propogation speed is concerned and are...
4870609 High speed full adder using complementary input-output signals  
The operation speed of a full adder is increased by avoiding the necessity of forming the inverse signal for adder operation and deleting the time required for passing through an inverter.
4866658 High speed full adder  
A high speed full adder circuit is shown to include logic circuitry responsive to the levels of the two digital signals to be added for: (a) immediately producing an appropriate carry signal when...
4853887 Binary adder having a fixed operand and parallel-serial binary multiplier incorporating such an adder  
Binary adder having a fixed operand and a parallel-serial binary multiplier incorporating such an adder. The multiplier comprises a dedicated adder, whose elements (transistors, logic gates, etc.)...
4839849 Ripple-carry adder  
An adder cell for a ripple-carry adder, suitable for use in an integrated circuit employing CMOS technology, has a gate arrangement for two input variables and a carry input signal, with outputs...
4831578 Binary adder  
A binary adder stage in which the two binary inputs are logically combined to produce the Exclusive-OR, the Exclusive-NOR, the NAND and the NOR functions of the two inputs. The carry-input signal...
4831570 Method of and circuit for generating bit-order modified binary signals  
A method of and a circuit for generating address signals, wherein a binary index signal and a binary base address signal are stored in index and address registers, respectively, whereupon the index...
4817030 CMOS full-adder stage  
To a prior art CMOS full-adder stage having sixteen transistors, a static inverter is added which consists of a P-type transistor and an N-type transistor, and the series combination (sc) of P- and...
Matches 1 - 50 out of 90 1 2 >