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7592835 |
Co-processor having configurable logic blocks
A co-processor system is provided that includes an array of configurable logic blocks (CLBs). Each CLB including a plurality of look-up tables and a plurality of adders. Each CLB may be dynamically...
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7555514 |
Packed add-subtract operation in a microprocessor
A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated...
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7428567 |
Arithmetic unit for addition or subtraction with preliminary saturation detection
An arithmetic unit for performing an arithmetic operation on at least first and second input operands, each of the input operands being separable into a first portion and a second portion, such as...
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7424507 |
High speed, low power, pipelined zero crossing detector that utilizes carry save adders
A zero crossing detector employs carry save adders combined with fully pipelined logic to provide two-bit, three-bit or four-bit zero crossing detection. The detector offers the advantages of very...
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7395302 |
Method and apparatus for performing horizontal addition and subtraction
A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory...
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7376691 |
Arithmetic and logic unit using half adder
The present invention discloses an ALU (Arithmetic Logic Unit) that can be operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using a half adder that uses a superconductor...
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7373369 |
Advanced execution of extended floating-point add operations in a narrow dataflow
A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and...
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7356554 |
Variable fixed multipliers using memory blocks
A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift...
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7322032 |
Methods and apparatus for scheduling operation of a data source
A computerized device has dynamically modifiable hardware, such as an ASIC, that performs queue-scheduling operations. The hardware incorporates a generic sorting processor (GSP) that is...
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7228325 |
Bypassable adder
An adder for adding a signal at a first input (A) and a second input (B) to produce an adder output (S) is disclosed. The adder comprises a bypass input (bypass) and a logic circuit,...
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7225218 |
Apparatus and methods for generating counts from base values
An apparatus for generating a plurality of counts is provided. A first adder is coupled to receive n least significant bits of a base count and a plurality of signals indicative of a plurality of...
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7213043 |
Sparce-redundant fixed point arithmetic modules
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive...
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7197528 |
Jacobian group element adder
An objective is to obtain a Jacobian group element adder that can calculate addition in a Jacobian group of a C ab curve at a high speed, and can enhance practicality of the C ab curve. An...
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7164290 |
Field programmable gate array logic unit and its cluster
The embodiments of the present invention relate to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the...
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7155473 |
High-speed parallel-prefix modulo 2n-1 adders
A parallel-prefix modulo 2 n −1 adder that is as fast as the fastest parallel prefix 2 n integer adders, does not require an extra level of logic to generate the carry values, and has a very...
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7139900 |
Data packet arithmetic logic devices and methods
New instruction definitions for a packet add (PADD) operation and for a single instruction multiple add (SMAD) operation are disclosed. In addition, a new dedicated PADD logic device that performs...
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7111166 |
Extending the range of computational fields of integers
An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the...
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7061268 |
Initializing a carry chain in a programmable logic device
A logic circuit includes a first series of logic elements. Each logic element has a look-up table (LUT) and a dedicated adder to implement an arithmetic mode in the logic element. The logic circuit...
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7058678 |
Fast forwarding ALU
An apparatus and method for performing fast arithmetic operations, including addition, in a pipelined circuit is described. The apparatus and method operating on a first binary number and a second...
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7013036 |
Image sensing apparatus and method of controlling image sensing
Signals obtained from a sensor array that includes a plurality of energy transducers are processed. A converter used in this processing generates a plurality of converted signals by applying...
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6988121 |
Efficient implementation of multiprecision arithmetic
The present invention provides an efficient implementation of multiprecision arithmetic, such as for a microprocessor. For example, an implementation of multiprecision arithmetic is provided that...
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6918024 |
Address generating circuit and selection judging circuit
An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address...
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6877069 |
History-based carry predictor for data cache address generation
An address translation logic and method for generating an instruction's operand address. The address generation logic includes an address generation circuit having adders that perform partial sum...
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6868432 |
Addition circuit for digital data with a delayed saturation operation for the most significant data bits
An addition circuit for digital data includes a digital adder for the addition of digital input data values present at data inputs of the digital adder to form a summation output data value, at an...
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6832234 |
In-place associative processor arithmetic
A method of performing in-place arithmetic, particularly addition and subtraction, on numbers stored in respective consecutive rows of an array processor that has two tags registers. In a first...
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6757703 |
Associative processor addition and subtraction
Methods of adding and subtracting sets of binary numbers using an associative processor. The inner loop over corresponding bits of the operands is executed in only three machine cycles. Only the...
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6754689 |
Method and apparatus for performing subtraction in redundant form arithmetic
A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from...
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6742013 |
Apparatus and method for uniformly performing comparison operations on long word operands
Using a subtraction without borrow operation, the first operand lowest order word is subtracted from a second operand lowest order word. If the result of the subtracting is not zero, then a zero...
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6668268 |
Method and apparatus for compiling dependent subtraction operations on arithmetic intervals
One embodiment of the present invention provides a system for compiling computer code to perform a subtraction operation between a first interval and a third interval to produce a resulting...
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6591285 |
Running-sum adder networks determined by recursive construction of multi-stage networks
A technique for physically implementing a running sum adder network and configuring the concomitant adder network of elements. A 2 k+1 ×2 k+1 adder network has the size 2 k+2 −k−3 and depth...
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6584156 |
LSI Architecture and implementation of MPEG video codec
Flexible VLSI architecture implements of MPEG video processing unit (VPU) for encoding and decoding. In encoding mode, VPU performs compression operations on digitized video input per MPEG...
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6557097 |
Linear vector computation
A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient...
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6546410 |
High-speed hexadecimal adding method and system
Adder circuitry is provided based on a reduced mathematical method to provide high-speed hexadecimal addition. A first adder adds the least significant binary digits of two hexadecimal numbers to...
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6542918 |
Prefix sums and an application thereof
A method for performing prefix sums, by including a prefix sum instruction in the instruction set of a microprocessor. Both general prefix summation, base-zero prefix summation and base-zero suffix...
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6505225 |
Adder logic circuit and processor
An adder logic circuit for performing an addition operation of a first numerical value and a second numerical value having a bit width narrower than that of the first numerical value is described....
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6493263 |
Semiconductor computing circuit and computing apparatus
Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the...
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6460066 |
50 MHz 40-bit accumulator with trigger capability
A triggerable, pipelined 40-bit high speed accumulator includes trigger and continuous modes which can be operated at 50 MHz clock frequency. The high speed accumulator can be combined with static...
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6446106 |
Seed ROM for reciprocal computation
A method and apparatus for performing a divide operation in a computer are described. The apparatus includes a first memory containing estimated reciprocal terms, and a second memory containing...
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6405233 |
Unaligned semaphore adder
A technique for receiving a first data from a storage location in which the first data is not stored fully aligned within processor data boundaries for data retrieval. The adder also receives a...
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6374281 |
Adder
An adder comprises: a comparator circuit 2 for comparing values of n input signals, each of which comprises 1-bit data, with first to n-th predetermined values which are different from each...
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6369610 |
Reconfigurable multiplier array
This invention provides a logic block comprising an mxn array of partial calculating circuits (where m≧2 and n≧2) operable to generate partial product components of an m-bit multiplicand x...
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6363408 |
Method and apparatus for summing selected bits from a plurality of machine vectors
An apparatus is provided for adding selected bits. The apparatus includes a hardware device having a plurality of ordered input terminals to receive binary signals for a portion of an ordered set...
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6334136 |
Dynamic 3-level partial result merge adder
The present invention comprises a method and apparatus that selectably performs either addition or subtraction on two N-nary operands to generate an intermediate, then final, N-nary final result....
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6330581 |
Apparatus and a method for address generation
The present invention provides an apparatus and a method for address generation. In one embodiment, an apparatus for an address generation unit of an ALU (Arithmetic Logic Unit) of a microprocessor...
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6301600 |
Method and apparatus for dynamic partitionable saturating adder/subtractor
An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The...
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6301597 |
Method and apparatus for saturation in an N-NARY adder/subtractor
An apparatus and method for performing saturating addition or subtraction on two signed or unsigned operands using N-NARY logic. The two operands may be selectably partitioned into 8-bit, 16-bit,...
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6223199 |
Method and apparatus for an N-NARY HPG gate
The present invention discloses an apparatus and method for performing carry propagate logic on two 1-of-4 two-bit addends to produce a 1-of-3 carry propagate indicator. The preferred embodiment of...
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6219688 |
Method, apparatus and system for sum of plural absolute differences
A method for forming a sum of the absolute value of the difference between each pair of numbers of respective first and second sets of numbers. The method includes forming the difference between a...
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6219687 |
Method and apparatus for an N-nary Sum/HPG gate
The present invention utilizes N-nary logic to implement an add function and a carry-lookahead function within the same gate, producing an N-nary sum and an N-nary HPG indicator.
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6216146 |
Method and apparatus for an N-nary adder gate
The present invention discloses a method and apparatus for adding two 1-of-N addends to produce a 1-of-N sum. In the preferred embodiment, the addends and sum comprise 1-of-4 logic signals.
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