Matches 1 - 19 out of 19
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7536430 Method and system for performing calculation operations and a device  
A method for performing calculation operations uses a pipelined calculation device comprising a group of at least two pipeline stages, at least one data interface for input of data, and at least...
7334011 Method and system for performing a multiplication operation and a device  
In a method for performing a multiplication operation between a first operand and a second operand the multiplication operation is divided into at least two suboperations. At least one of the...
6604120 Multiplier power saving design  
A digital parallel multiplier has encoders for each segmented bit pair of the multiplier input data which select one of 4 coefficients, based on the sum of the bit pair, that are then applied to...
6353843 High performance universal multiplier circuit  
A partitioned multiplier circuit which is designed for high speed operations. The multiplier of the present invention can perform one 32×32 bit multiplication, two 16×16 bit multiplications...
6183122 Multiplier sign extension  
A digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then...
6175912 Accumulator read port arbitration logic  
A processor architecture having an accumulator register file with multiple shared read and/or write ports. Depending on the instruction, each port can be used to communicate with a different data...
6122320 Circuit for motion estimation in digitized video sequence encoders  
The circuit for motion estimation in digitised video sequence encoders comprises at least an integrated circuit component (IM, IM1 . . . IMn) which is arranged to perform either the function of...
6085214 Digital multiplier with multiplier encoding involving 3X term  
A digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then...
6052706 Apparatus for performing fast multiplication  
In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the...
6004022 Product sum operation apparatus  
A product sum operation apparatus in which an increase in the circuit scale of the product sum operation apparatus can be suppressed and the operation speed can be increased even when the number of...
5870322 Multiplier to selectively perform unsigned magnitude multiplication or signed magnitude multiplication  
A multiplier for selectively performing an unsigned magnitude multiplication or a signed magnitude multiplication with a modified Booth algorithm for a multiplication operation. It includes a...
5787029 Ultra low power multiplier  
A multiplier using a modified Booth algorithm dissipates power proportional to the magnitude of one of the operands, and logic races are eliminated using iterative networks.
5761106 Horizontally pipelined multiplier circuit  
A multiplier circuit (300, 400, 500, 600) uses a horizontal pipelining of the circuitry (301, 401, 501, 601) in order to reduce the number of gate-drain delays within the various data paths through...
5636155 Arithmetic processor and arithmetic method  
An arithmetic processor employs two modes of nonpipeline operation and pipeline operation, and is provided with a redundant binary multiplication part for generating redundant binary multiplied...
5515309 1-bit adder and multiplier containing a 1-bit adder  
A one-bit adder includes a carry stage and an adding stage and is constructed in a fast CMOS complementary pass transistor logic with complementary analog CMOS switches in the adding stage which...
5220525 Recoded iterative multiplier  
A recorded iterative multiplier (20) performs an unsigned multiplication operation quickly and with a minimal amount of added circuitry. Multiplier (20) includes a Modified Booth recoder (34) and a...
5150322 Mixed-radix serial/parallel multipliers  
A serial/parallel multiplier for the multiplication of a coefficient word with a data word of which the bits are broadcast n at a time where n is at least three. The structure comprises a plurality...
4965762 Mixed size radix recoded multiplier  
An array multiplier utilizing a predetermined recoding algorithm minimizes operating speed by using two different radices. Special product terms must be formed to implement the recording algorithm....
4807175 Booth's multiplier  
In Booth's method of calculating a product of a multiplicand X and a multiplier Y, Y is divided into plural partial multipliers PP i (Y i , Y i +1, Y i +2); partial products PD i are formed...
Matches 1 - 19 out of 19