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7587443 Digital signal processor with efficient multi-modal multiplier  
A digital signal processor architecture allows the digital signal processor to be used efficiently for multiplying words which are longer than the word length for which the architecture is...
7543008 Apparatus and method for providing higher radix redundant digit lookup tables for recoding and compressing function values  
An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits...
7519648 Encoder for a multiplier  
An encoder of a multiplier may include an operator generating unit for encoding a plurality of received multiplier data to output a plurality of operators. The encoder may include a partial-product...
7483935 System and method to implement a matrix multiply unit of a broadband processor  
The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a...
7480691 Arithmetic device for multiple precision arithmetic for Montgomery multiplication residue arithmetic  
In an arithmetic device which performs a multiplication of a multiplicand A and a multiplier B expressed by bit patterns using a secondary Booth algorithm, an encoder selects a partial product...
7433912 Multiplier structure supporting different precision multiplication operations  
A unified data flow is provided that allows multiplication of SIMD and non-SIMD multiplies in one multiplier. The multiplies may be both integer and floating point operations. The multiplier is...
7334200 Low-error fixed-width modified booth multiplier  
A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a...
7308471 Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding  
A digital circuit including a Booth encoder having inputs for receiving a plurality of adjacent bits of a first binary input number, and an encoder control input for allowing selection between...
7308470 Smaller and lower power static mux circuitry in generating multiplier partial product signals  
A multiplier circuit to receive a multiplier and a multiplicand comprises at least one Booth encoder circuit to encode a plurality of multiplier bits into four encoded outputs. The encoded outputs...
7272624 Fused booth encoder multiplexer  
A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which...
7177894 Switching activity reduced coding for low-power digital signal processing circuitry  
A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a...
7139787 Multiply execution unit for performing integer and XOR multiplication  
A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for summing...
7096246 Arithmetic unit for multiplying a first quantity X by a second quantity Y  
An arithmetic unit for multiplying a first quantity x by a second quantity y, the arithmetic unit including a Booth coder having a plurality of inputs for receiving a plurality bits of the second...
7069290 Power efficient booth recoded multiplier and method of multiplication  
In the multiplier, a partial product circuit generates a partial product based on a multiplicand operand and outputs of a Booth recoder circuit, which operates on a multiplier operand. The partial...
7043517 Multiply accumulator for two N bit multipliers and an M bit addend  
A multiply accumulator performs a multiplication-and-addition operation for a first multiplier with N bits, a second multiplier with N bits, and an addend with M bits, wherein M is larger than 2N....
7024445 Method and apparatus for use in booth-encoded multiplication  
A new partial product bit generator is used to generate a partial product bit PPj i . In some embodiments, the partial product bit generator generates the partial product bit PPj i from...
6973471 Method and apparatus for implementing signed multiplication of operands having differing bit widths without sign extension of the multiplicand  
A multiplier ( 42 ) forms a product from two signed operands without performing a sign extension of the multiplicand (A). A modified Booth's recoding of the multiplier operand (B) is begun...
6957244 Reduced-width low-error multiplier  
This invention discloses a reduced-width, low-error multiplier that can be used in Digital Signal Processing (DSP). Specifically, this invention relates to a reduced-width, low-error multiplier...
6950840 Noise invariant circuits, systems and methods  
The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a...
6877022 Booth encoding circuit for a multiplier of a multiply-accumulate module  
A Booth encoding circuit includes a plurality of cells ( 202 a- 202 d ), in which at least one of the cells ( 202 c ) includes a plurality of inputs. The cell also includes a first plurality of...
6816877 Apparatus for digital multiplication using redundant binary arithmetic  
A digital multiplication apparatus and method adopting redundant binary arithmetic is provided. In this digital multiplication apparatus, when two numbers X and Y are multiplied using a radix-2k...
6785702 Energy saving multiplication device and method  
An energy saving multiplication device and its method is disclosed. The multiplication device includes a dynamic range determination unit, a Booth encoding/decoding unit and a counter array. The...
6711633 4:2 compressor circuit for use in an arithmetic unit  
A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive...
6704762 Multiplier and arithmetic unit for calculating sum of product  
In a case of performing a multiplication operation with low accuracy, a value of the most significant bit included in the least significant half the bits of a multiplier is replaced with “0”. A...
6684236 System of and method for efficiently performing computations through extended booth encoding of the operands thereto  
A system of and method for extended Booth encoding of two binary numbers, K and L. A stage of the encoder receives K[2n+1], K[2n], L[2n+1], and C[n−1], N−1≧n≧0, with N being the length of...
6647404 Double precision floating point multiplier having a 32-bit booth-encoded array multiplier  
A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is...
6622154 Alternate booth partial product generation for a hardware multiplier  
In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware...
6604120 Multiplier power saving design  
A digital parallel multiplier has encoders for each segmented bit pair of the multiplier input data which select one of 4 coefficients, based on the sum of the bit pair, that are then applied to...
6463453 Low power pipelined multiply/accumulator with modified booth's recoder  
A low power high speed multiply/accumulator ( 100 ) utilizes a modified Booth's recoder ( 120 ) to identify situations to power down the partial product array ( 130 ). The modified Booth's recoder...
6434587 Fast 16-B early termination implementation for 32-B multiply-accumulate unit  
An embodiment of the present invention is a mixed length encoding unit. The mixed length may be a 12/16 bits (12/16-b) encoding algorithm within a multiply-accumulate (MAC). The mixed length...
6393554 Method and apparatus for performing vector and scalar multiplication and calculating rounded products  
A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands...
6366944 Method and apparatus for performing signed/unsigned multiplication  
An apparatus for performing signed and unsigned multiplication is presented comprising a computation cell to generate a plurality of product terms, a compressor, coupled to the computation cell,...
6347326 N bit by M bit multiplication of twos complement numbers using N/2&plus 1 X M/2&plus 1 bit multipliers  
The operands of an N×M bit multiplication are partitioned into N/j+1 and M/k+1 bit signed submultiples. The most significant submultiple is assigned the sign of the operand, while each of the less...
6301599 Multiplier circuit having an optimized booth encoder/selector  
An improved Booth encoder/selector circuit having an optimized critical path. The Booth encoder has a number of inverters coupled to several of the input multiplier bits. The inverted/non-inverted...
6272513 Multiplying device  
A multiplying device operates for implementing multiplication between multiplicand data and multiplier data in a two's complement representation form. Each of the multiplicand data and the...
6202078 Arithmetic circuit using a booth algorithm  
A booth decoder decodes A or -A according to a booth algorithm, depending upon whether A×B or -A×B should be multiplied. A partial multiplier/partial adder circuit 30 generates partial products...
6183122 Multiplier sign extension  
A digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then...
6167422 Booth multiplication structure which selectively integrates the function of either of incrementing or negating with the function of booth multiplication  
A combination has a booth recoder with at least three input lines; two input lines corresponding to two bits of a multiplier and one input line being an increment select line. In one embodiment,...
6157939 Methods and apparatus for generating multiplicative inverse product  
An multiplier circuit that generates a negate product -B*C quickly without requiring a separate negate operation. This multiplier circuit uses partial product multiplication and any of a variety of...
6144980 Method and apparatus for performing multiple types of multiplication including signed and unsigned multiplication  
A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and may include a partial product...
6141674 Reducing the hardware cost of a bank of multipliers by combining shared terms  
A circuit that performs the function of a bank of multipliers while reducing hardware costs includes shared term generator that generates a set of shared terms in response to an input value. The...
6131107 Fast determination of carry inputs from lower order product for radis-8 odd/even multiplier array  
A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3...
6108622 Arithmetic logic unit controller for linear PCM scaling and decimation in an audio decoder  
An audio decoder converts a linear PCM audio data packet into two concurrently provided digital audio sample sequences: a high-quality sequence and a decimated sequence. In one embodiment, the...
6085214 Digital multiplier with multiplier encoding involving 3X term  
A digital parallel multiplier having encoders for each segmented bit pair of the multiplier input data and which selects one of 4 coefficients, based on the sum of the bit pair, that are then...
6081823 Circuit and method for wrap-around sign extension for signed numbers  
A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in...
6035319 Parallel-serial multiplier and accumulator  
An improved parallel-serial multiplier and accumulator for multiplying a digital multiplicand and a multiplier resulting in a product that is added to an accumulator input. The parallel-serial...
6035318 Booth multiplier for handling variable width operands  
A circuit for generating partial products for variable width multiplication operations is provided. According to an embodiment of the present invention, the circuit includes a plurality of partial...
6004022 Product sum operation apparatus  
A product sum operation apparatus in which an increase in the circuit scale of the product sum operation apparatus can be suppressed and the operation speed can be increased even when the number of...
5986587 Redundant binary code converting circuit and multiplication circuit using same  
A redundant binary code conversion circuit consists of first to third RBC conversion circuits 261 to 263. The circuit 261 consists of decoders 30 to 38 of the same construction, the circuit 262...
5957999 Booth multiplier with squaring operation accelerator  
A multiplier which uses Booth recoding to multiply large word length operands. A first operand is fully loaded into a shift register. The loading of the second operand is then begun, with the...
Matches 1 - 50 out of 133 1 2 3 >