Matches 1 - 50 out of 99 1 2 >
Match Document Document Title
7139788 Multiplication logic circuit  
A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which...
6938061 Parallel counter and a multiplication logic circuit  
A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is...
RE38387 Multiplier circuit for multiplication operation between binary and twos complement numbers  
A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are...
6567834 Implementation of multipliers in programmable arrays  
Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of...
6535646 Discrete cosine transform method and apparatus  
A linear transform apparatus for implementing a linear transform on input data values to produce linear transformed output data, the apparatus comprising: input means for inputting input data...
6530011 Method and apparatus for vector register with scalar values  
A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and...
6490608 Fast parallel multiplier implemented with improved tree reduction schemes  
Parallel multipliers and techniques for reducing Wallace-trees in parallel multipliers to achieve fewer reduction stages. The parallel multipliers of the present invention, in one embodiment,...
6470371 Parallel multiplier  
An improved parallel multiplier capable of operating an addition operation by connecting a plurality of dividers sequentially, thus providing more simple circuit and reducing operating time...
6385634 Method for performing multiply-add operations on packed data  
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored...
6202078 Arithmetic circuit using a booth algorithm  
A booth decoder decodes A or -A according to a booth algorithm, depending upon whether A×B or -A×B should be multiplied. A partial multiplier/partial adder circuit 30 generates partial products...
6167421 Methods and apparatus for performing fast multiplication operations in bit-serial processors  
Bit-serial processors quickly multiply multiple-bit operands using significantly fewer clock cycles as compared to conventional bit-serial implementations. Exemplary embodiments process groups of...
6122655 Efficient use of inverting cells in multiplier converter  
A multiplier generates an array of partial products. The partial products are reduced in a converter having cells defining rows and columns. Cells adjacent to adders alternate between a cell that...
6066178 Automated design method and system for synthesizing digital multipliers  
A computer-based method and system is disclosed that automates the design and layout of digital multiplier circuits. The preferred method utilizes an automatic design generator having a user...
6035316 Apparatus for performing multiply-add operations on packed data  
A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit...
6026483 Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands  
A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and comprises a partial product...
5978827 Arithmetic processing  
In a processor for performing operations including an addition of a plurality of multiple bit data, values on common places of a plurality of multiple bit data are entered in parallel into number...
5963744 Method and apparatus for custom operations of a processor  
Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time...
5944775 Sum-of-products arithmetic unit  
A sum-of-products arithmetic unit includes a coefficient register, a data register, a multiplier, an adder, and a data bus used for the transfer of data to and from an external unit. Provision is...
5928317 Fast converter for left-to-right carry-free multiplier  
A multiplier generates an array of partial products. The partial products are reduced in the more significant side of the array assuming a carry-out from the less significant side of the array as...
5914892 Structure and method of array multiplication  
A structure and method for forming multiplication of a b-bit multiplicand X and a b-bit multiplier Y to generate a product P is disclosed. The present invention includes cells C mn configured in a...
5883825 Reduction of partial product arrays using pre-propagate set-up  
There is disclosed a converter for summing inputs includes first, second, third and fourth adders. Each of the adders is adapted to receive a carry-in and to provide as outputs a carry-out and a...
5764558 Method and system for efficiently multiplying signed and unsigned variable width operands  
A plurality of multipliers for multiplying numbers having B number of bits are provided for multiplying A-operands having B number of bits by a B-operand having B number of bits. Pairs of A- and...
5721697 Performing tree additions via multiplication  
A multiplier is modified to perform a tree addition. A first value is input to the multiplier in place of a first multiplicand. The first value is a concatenation of addends upon which the tree...
5699286 Wavelet transform processor using a pipeline with a bit unit  
The present invention relates to a wavelet transform processor, and more particularly, to a wavelet transform processor using a pipeline with a bit unit, capable of being effectively used in the...
5586071 Enhanced fast multiplier  
A Wallace-type binary tree multiplier in which the partial products of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels comprised of full...
5521856 Multiplier capable of calculating double precision, single precision, inner product and multiplying complex  
An AND gate inputs the most significant bit of a lower word of an multiplicand or "0" to an input terminal of the least significant bit of Booth's decoders to which an upper word of the...
5473558 Method for generating hardware description of multiplier and/or multiplier-adder  
A method for generating a hardware description of a multiplier/multiplier-adder for integrating a signal processing circuit includes the steps of acquiring input parameters such as a word length of...
5473559 Hardware implemented multiplier  
A sign inverting Booth encoder included in an encoding circuit generates a control signal designating a partial product having a sign different from that designated by an output signal generated...
5457646 Partial carry-save pipeline multiplier  
A pipeline multiplier is used for multiplying a multiplicand to a multiplier. The pipeline multiplier includes a plurality of adder stages each adder stage includes a partial product processor for...
5446909 Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand  
Binary multiplication is performed with existing data processing apparatus to which only minor modifications are required. One operand and a partial product are stored in existing latches of a CPU....
5442799 Digital signal processor with high speed multiplier means for double data input  
The present invention improves a digital signal processor, more particularly, calculation methods for motion compensation in reduceing a required amount of calculations when an amount of distortion...
5343417 Fast multiplier  
A Wallace-type binary tree multiplier in which the partial products of a multiplicand and a multiplier are produced and then successively reduced using a plurality of adder levels comprised of full...
5299146 Matrix arithmetic circuit  
A matrix arithmetic circuit includes an address generator, a first multiplier, a second multiplier, and an accumulator. The address generator generates addresses of first, second, and third...
5283755 Multiplier employing carry select or carry look-ahead adders in hierarchical tree configuration  
A multiplication circuit for a floating point digital processing system includes a partial products generator and a carry adder circuit for determining a product resulting from multiplication of an...
5181184 Apparatus for multiplying real-time 2's complement code in a digital signal processing system and a method for the same  
A pipeline multiplier capable of multiplying 2's complement codes is disclosed. The multiplier operates the multiplication faster than the conventional one by receiving a first predetermined-bit of...
5166895 Input-weighted transversal filter  
Tap arithmetic units and first delay circuits are arranged alternately. Each of the tap arithmetic units has a full-adder array for multiplying an input signal which has been sampled at regular...
5159568 High speed parallel multiplier circuit  
The binary multiplier circuit for obtaining a product of a M-bit multiplier and a N-bit multiplicand includes a multiplier circuit which produces a matrix of original summand bits having M rows and...
5153849 Multiplier having an optimum arrangement of anding circuits and adding circuits  
A multiplier in which m-1 place multiplicands can be operated with the multiplier with n-1 place multiplier factors that are represented as binary numbers. In order to achieve a regularly...
5151875 MOS array multiplier cell  
A complementary metal-oxide semiconductor (CMOS) array multiplier cell comprising two CMOS equivalence circuits for sum generation, two pass transistors and an inverter for carry generation, and a...
5121352 Multiplier-accumulator circuit array operable in multiple modes  
A high-speed circuit that performs unsigned mode, two's complement mode, and mixed mode multiplication-accumulation with equal facility. The invention incorporates a high degree of regularity and...
5101372 Optimum performance standard cell array multiplier  
A cell array multiplier uses unique adder interconnections to increase the multiplier output speed. More specifically, adder connections for each column of the multiplier are generated by...
5095457 Digital multiplier employing CMOS transistors  
A digital multiplier for multiplying a binary N bit multiplicand by a binary N bit multiplier. The digital multiplier comprises a plurality of AND gates in which each digit of the mutliplicand is...
5031137 Two input bit-serial multiplier  
A reduced adder precision apparatus uses two adders to produce a serial output product of two serial input digital numbers. The multiplier operates on a bit by bit basis, beginning with the least...
5010510 Multiplying unit circuit  
A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and...
4991131 Multiplication and accumulation device  
A multiplication device is provided for forming the product of a first and a second N-bit input binary number. The multiplication device receives the two input binary numbers and forms a two's...
4982355 Low-power parallel multiplier  
A parallel multiplier consists of a systolic array of AND gates and full adders organized in stages so that each stage generates a partial product, adds it to the preceding partial products, and...
4974198 Vector processing system utilizing firm ware control to prevent delays during processing operations  
A vector processing system prevents delays in reading microinstructions from a control memory during processing operations. The vector processing system permits a second microinstruction to be read...
4905179 CMOS cell for logic operations with fast carry  
The elementary adder, as far as carry propagation is concerned, has two circuit branches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated when two operands have...
4872134 Signal processing integrated circuit for row and column addition of matrices of digital values  
A signal-processing circuit performs a cosine type transformation (double addition in rows and columns) of values of a matrix of n rows and n columns. An architecture is proposed with a row...
4852037 Arithmetic unit for carrying out both multiplication and addition in an interval for the multiplication  
In an arithmetic unit comprising a partial product circuit for calculating a plurality of partial products for two numbers and a Wallace tree responsive to the partial products for producing a...
Matches 1 - 50 out of 99 1 2 >