Match

Document 
Document Title 

9032009 
Multiplier circuit
A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the... 

8918446 
Reducing power consumption in multiprecision floating point multipliers
Methods and apparatus relating to reducing power consumption in multiprecision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in... 

8886696 
Digital signal processing circuitry with redundancy and ability to support larger multipliers
Digital signal processing (“DSP”) circuit blocks that include multipliers of a certain basic size are augmented to enable the DSP block to perform multiplications that are larger than the basic... 

8788562 
Large multiplier for programmable logic device
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier... 

8667046 
Generalized programmable counter arrays
A Generalized Programmable Counter Array (GPCA) is a reconfigurable multioperand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to... 

8639738 
Method for carry estimation of reducedwidth multipliers
A lowerror reducedwidth multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies... 

8577172 
Reconfigurable module and method of implementing this reconfigurable module for performing morphological operations
The invention provides a reconfigurable module allowing morphological operations to be carried out for image processing. The module includes an operational block having five inputs, three outputs,... 

8566384 
Multiplicative group counter
Systems and methods are provided for efficiently counting detected events via a multiplicative group counter. An equivalent class polynomial congruent with a first of a plurality of elements... 

8495125 
DSP engine with implicit mixed sign operands
A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit... 

8468193 
Binary number multiplying method and circuit
A multiplier and a method multiply, using an array of adders, two binary numbers X and Y defining a matrix [Eni=xn−i·yi], wherein the initial matrix [Eni=xn−i·yi] is transformed into a matrix... 

8468192 
Implementing multipliers in a programmable integrated circuit device
The number of multipliers of a particular size that are required to perform a multiplication larger than that size is reduced. In the example of a 36bitby36bit multiplication, the number of... 

8438207 
Adaptive precision arithmetic unit for error tolerant applications
Two processtolerant arithmetic circuit architectures are implemented to develop functional blocks for errortolerant applications such as FIR filters and FFT blocks. The resulting blocks may... 

8438208 
Processor and method for implementing instruction support for multiplication of large operands
A processor including instruction support for implementing largeoperand multiplication may issue, for execution, programmerselectable instructions from a defined instruction set architecture... 

RE44190 
Long instruction word controlling plural independent processor operations
A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first... 

8386553 
Large multiplier for programmable logic device
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier... 

8364738 
Programmable logic device with specialized functional block
In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are... 

8364741 
Motioncompensating device with booth multiplier that reduces power consumption without increasing the circuit size
A multiplier includes an operation unit that adds or subtracts a first group selected from a current input data, and a second group selected from a next input data corresponding to the first group... 

8352532 
Circuit structure for multiplying numbers using lookup tables and adders
A circuit structure efficiently multiplies a first and second number. The circuit structure includes multipliers for the pairs of threebit digits of the first number and threebit digits of the... 

8352533 
Semiconductor integrated circuit in in a carry computation network having a logic blocks which are dynamically reconfigurable
There is provided a semiconductor integrated circuit including: a plurality of first logic blocks which are reconfigurable, the plurality of first logic blocks inputting data of a first bit width... 

8307023 
DSP block for implementing large multiplier on a programmable integrated circuit device
A programmable integrated circuit device includes a plurality of specialized processing blocks. Each specialized processing block may be small enough to occupy a single row of logic blocks. The... 

8280941 
Method and system for performing calculations using fixed point microprocessor hardware
A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at... 

8229991 
Processor core and multiplier that support a multiply and difference operation by inverting sign bits in booth recoding
The present invention provides processing systems, apparatuses, and methods that support both general processing processor (GPP) and digital signal processor (DSP) features, such as vector and... 

8229109 
Modular reduction using folding
Techniques are described to determine N mod M, where N is a number having a width of nbits, and M is a number having a width of mbits. The techniques, generally, involve determining N′=Nrt2f mod... 

8209369 
Signal processing apparatus and method for performing modular multiplication in an electronic device, and smart card using the same
Provided is an apparatus for encryption/decryption and electronic signature in a mobile communication environment. A signal processing apparatus, performing modular multiplication in an electronic... 

8180822 
Method and system for processing the booth encoding 33RD term
A computer system for computing a binary operation involving a first term multiplied by a second term resulting in a product, where the product is conditionally added to a third term in a central... 

8150903 
Reconfigurable arithmetic unit and highefficiency processor having the same
Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an... 

8112468 
Method and apparatus for performing an operation with a plurality of suboperations in a configurable IC
Some embodiments provide a method of performing a mathematical operation on a set of operands. The mathematical operation includes several suboperations. The method examines several bits of at... 

8041758 
Multiplier and arithmetic unit
A multiplier has a multiplication array in which partial products are generated by performing multiplication between a multiplier and a multiplicand, and a partial product control circuit which... 

7930337 
Multiplying two numbers
Techniques are described to multiply two numbers, A and B. In general, multiplication is performed by using Karatsuba multiplication on the segments of A and B and adjusting the Karatsuba... 

7930336 
Large multiplier for programmable logic device
A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier... 

7912890 
Method and apparatus for decimal number multiplication using hardware for binary number operations
According to embodiments of the subject matter disclosed in this application, decimal floatingpoint multiplications and/or decimal fixedpoint multiplications may be implemented using existing... 

7912891 
High speed low power fixedpoint multiplier and method thereof
Provided are a high speed and low power fixedpoint multiplier and method thereof. The multiplier includes: a partial product calculation unit for dividing input data into a plurality of bit... 

7895255 
Method and apparatus for performing a multiplication or division operation in an electronic circuit
A multiplication or division operation X·K or X·1/K is performed in an electronic circuit. A software circuit area of the circuit calculates a digit shift sv such that psv is an approximate value... 

7856467 
Integrated circuit including at least one configurable logic cell capable of multiplication
The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial... 

7853635 
Modular binary multiplier for signed and unsigned operands of variable widths
A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first... 

7840629 
Methods and apparatus for providing a booth multiplier
Methods and apparatus for converting a radix 2 multiplier to respective groups of radix 4 encoded bits representing numbers of the group consisting of −2, −1, 0, 1, 2, wherein the set of encoded... 

7840628 
Combining circuitry
A combining circuit and method combines a plurality of terms in a multiplier circuit. The combining circuit includes a first circuit, arranged to receive a first set of the plurality of terms and... 

7818361 
Method and apparatus for performing two's complement multiplication
Some embodiments provide a novel way of performing a signed multiplication. Each individual bit of a first operand is multiplied by every bit of a second operand to generate partial multiplication... 

7797365 
Design structure for a booth decoder
A design structure for a Booth decoder is provided. The Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second... 

7797364 
Booth decoder apparatus and method
A Booth decoder may comprise three circuits that run in parallel. A first circuit is used to generate a shift control signal output. A second circuit is used to generate a zero control signal... 

7769797 
Apparatus and method of multiplication using a plurality of identical partial multiplication modules
A multiplication apparatus including a multiplier and multiplicand extractor for dividing the multiplicand into partial multiplicands and dividing the multiplier into partial multipliers, and for... 

7765249 
Use of hybrid interconnect/logic circuits for multiplication
Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions... 

7725522 
Highspeed integer multiplier unit handling signed and unsigned operands and occupying a small area
A highspeed integer multiplier unit multiplying operands, wherein each operand can be either signed or unsigned. Type data is received for each operand which indicates whether the corresponding... 

7685222 
Power of two multiplication engine
A multiplication engine is described in which a decision threshold engine utilizes a Yadder powers of two shift table to iteratively generate shiftadd combinations. The shiftadd combinations... 

7680474 
Superconducting digital mixer
Digital mixers which permit mixing of asynchronous signals are constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ nondestructive readout cell... 

7672989 
Large number multiplication method and device
A signed multiplication method and a corresponding device for multiplying a first multiplicand with a second multiplicand. The device stores the first multiplicand in a first register as a first... 

7668896 
Data processing apparatus and method for performing floating point multiplication
The first and second nbit significands are multiplied producing a pair of 2nbit vectors, and half adder logic produces a corresponding plurality of carry and sum bits. A product exponent is... 

7599981 
Binary polynomial multiplier
A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations. To this end, the multiply unit may include an input data path that receives input... 

7587443 
Digital signal processor with efficient multimodal multiplier
A digital signal processor architecture allows the digital signal processor to be used efficiently for multiplying words which are longer than the word length for which the architecture is... 

7567998 
Method and system for multiplier optimization
Described herein is a method and system for multiplier optimization. A gate count savings that does not introduce additional quantization error can be achieved with this method and system. By... 