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4748582 
Parallel multiplier array with foreshortened sign extension
A compact rectangular parallel multiplier array of Booth summation cells includes along a left edge a cell which reduces to two the number of signextension bits sufficient to generate subsequent... 

4736333 
Electronic musical instrument
An array of universal processing elements (UPEs) may be interconnected through a switching matrix in response to control words which are in turn produced by a programmed digital computer in... 

4722068 
Double precision multiplier
A double precision multiplyer for performing the multiplication of two double precision data using a 2's complement single precision multiplier. The 2n1 bit double precision data is divided into... 

4718031 
Multiplying circuit
In a multiplying operation, a first partial product corresponding to multiplication of the multiplicand by even multipliers can be produced by a shifting operation, while a second partial product... 

4706211 
Digital multiplying circuit
A digital multiplying circuit in a parallel multiplying circuit which can multiply an input which changes at a high data rate by the pipeline processing. A multiplicand is inputted to this... 

4686645 
Pipelined systolic array for matrixmatrix multiplication
A digital data processor for matrix/matrix multiplication includes a systolic array of nearest neighbor connected gated full adders. The adders are arranged to multiply two input data bits and to... 

4680727 
Complex multiplier for binary two's complement numbers
A method and apparatus for multiplying two digital pairings representing complex numbers is described. The method includes preloading a memory with contents based on the second complex combination... 

4644488 
Pipeline active filter utilizing a booth type multiplier
Multiplier units of the modified Booth decoder and carrysave adder/full adder combination are used to implement a pipeline active filter wherein pixel data is processed sequentially, and each... 

4639857 
Digital data processor incorporating an orthogonally connected logic cell array
The invention provides a digital data processor which has been systemetized down to bit level. The processor includes a regular array of identical processing cells which perform a logic operation... 

4636773 
Binarily weighted pulse width digitaltoanalog converter
A digitaltoanalog converter system for converting a digital input signal having parallel words, each word including multibit groups of weighted significance, and which is provided at an input... 

4598382 
Multiplying circuit
A multiplying circuit comprises an array circuit for producing a product of a multiplicand and multiplier by adding respective partial products together each of a multiplicand in each bit and a... 

4594680 
Apparatus for performing quadratic convergence division in a large data processing system
A binary division circuit for use in a large data processing system is disclosed which performs division with floating or fixed point numbers. It includes a multiplier unit which is modified to... 

4594679 
High speed hardware multiplier for fixed floating point operands
A high speed multiplier unit for multiplying both fixed point and floating point operands is disclosed and claimed. This multiplier unit is a system level functional unit which allows floating... 

4589085 
Hardware multiplier processor
A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor... 

4580229 
Method and apparatus for control of an articulated robot
An apparatus for controlling an articulated robot comprises coordinate transforming portions (5 to 8 and 18) and a calculating portion (9) for equation of motion. The coordinate transforming... 

4573136 
Sumofproducts multiplier with multiple memories and reduced total memory size
In a sumofproducts multiplier, such as is used in a digital filter, it is desired to be able to produce the sum of a number of independent multiplications of binary numbers each representing a... 

4571701 
Integrated circuit fast multiplier structure
There is disclosed a multiplier structure including elementary multipliers and a matrix of binary adder cells of the highspeed carry propagation type associated with the elementary multipliers.... 

4566075 
Table lookup multiplier employing compressed data read only memory
A multiplier circuit including a readonly memory containing a table of products for digits of a multiplicand and multiplier. The multiplier circuit will produce the product when a multiplicand... 

4566076 
Method of attenuating a digital signal and device for carrying out said method
In the method of attenuating or amplifying digital signal values as described herein the desired modification is realized in two steps.A coarse attenuation or amplification in steps of 6 dB is... 

4564920 
Multiplier with hybrid register
An integratedcircuit CPU saves layout space by employing the Address Register as the Extension Register for multiplication operations, the Address Register being modified to include shifting... 

4556948 
Multiplier speed improvement by skipping carry save adders
A complement carry technique and a staged skipping technique are employed for multipliers using four or more stages of carry save adders, to allow slower bits to skip past a stage while faster... 

4555768 
Digital signal processing system employing logarithms to multiply and divide
A digital signal processing system applies numbers to the multiplied or divided to address a memory storing a logarithm table to produce the logarithms of the numbers. These logarithms are added... 

4547862 
Monolithic fast fourier transform circuit
A fast Fourier transform circuit formed on a single chip, including a fast multiplieraccumulator circuit which, in the preferred embodiment, employs a modified form of Booth's algorithm, an adder... 

4546446 
Digital processing circuit having a multiplication function
In a Booth's algorithm multiplication circuit, a multiplicand is set in a multiplication register and a multiplier is set in a multiplier shiftregister. Consecutive bits of the multiplier are... 

4528641 
Variable radix processor
A variable radix processor is constructed on 1.25 micrometer CMOS/SOS. The processor, based upon a predetermined algorithm, is constructed to process radix 2 to 7 data wherein the data is input in... 

4507748 
Associative processor with variable length fast multiply capability
An associative processor is described wherein an array of associative processing cells is configured to achieve variable length multiplication of numbers, such as binary two's complement numbers,... 

4507749 
Two's complement multiplier circuit
A multiplication circuit includes a multiplying unit for multiplying a signed multiplier X represented in terms of the two's complement of n bits by a signed multiplicand Y represented in terms of... 

4495593 
Multiple bit encoding technique for combinational multipliers
A four member encoding set is disclosed which allows the construction of combinational monolithic multipliers with a significant reduction in the number of devices required. The reduced device and... 

4475167 
Fast coefficient calculator for speech
A digital circuit to approximate the product of two numbers by shifting the bits in one number to higher significance positions by an amount equal to the bit position of the most significant "one"... 

4449194 
Multiple point, discrete cosine processor
A discrete cosine processor for video signals and the like wherein each term of a discrete cosine transform matrix is approximated by a power of 2 terms so that all mathematical steps are... 

4441158 
Arithmetic operation circuit
There is disclosed an arithmetic operation circuit including an adder for performing a multiplication and a division. A one stage arithmetic cell group is formed by connecting eight arithmetic... 

4366549 
Multiplier with index transforms modulo a prime or modulo a fermat prime and the fermat prime less one
An asynchronous dataprocessing system for multiplying two binary numbers, by a use of readonly memories storing tables of data for transforming the numbers into exponents of a prime number. The... 

4322810 
Digital filters with reduced multiplier circuitry
A digital filter comprises a circuit means for applying a plurality of binary coded weights to a binary coded input data. The circuit means is constructed such that any of integer amounting to the... 

4313174 
ROMBased parallel digital arithmetic device
A fullyparallel digital arithmetic device for obtaining the square, C2, of a value, C, via parts of the value C and involving a reduction in memory requirements. Three square function ROM's are... 

4293922 
Device for multiplying binary numbers
A fast, parallel operating device for multiplying binary coded numbers. The numbers are divided into groups of n bits of directly successive significance levels. Subsequently, all feasible... 

4291387 
Analog to digital conversion weighting apparatus
A bucket brigade A/D weighting function multiplier which provides a simultaneous A/D conversion and multiplication by a weighting function in a continuous pipe line fashion, is disclosed. Each... 

4283770 
Signal processor for digital echo canceller
A processor for an echo canceller generates an estimate of an actual echo on an echo path and applies the same to a subtractor circuit in the path to cancel the echo. To generate the echo... 

4276607 
Multiplier circuit which detects and skips over trailing zeros
This invention is directed at an apparatus and method for detecting zero operand information and which also serves to detect trailing zeros. This circuit has application in computer circuitry,... 

4269101 
Apparatus for generating the complement of a floating point binary number
A complementer for floating point binary numbers utilizes two digital logic decision rules selected by the value of the power of the input number. The first decision rule is selected for an input... 

4229800 
Round off correction logic for modified Booth's algorithm
A round off correction logic circuit is disclosed for inclusion within a floating point arithmetic binary digital multiplier implementing a modified Booth's algorithm for generating a final... 

4216531 
Finite field multiplier
A multiplier for use with polynomials in an error correction system wherein the multiplier and multiplicand are first encoded from m bits to N bits, where N is greater than m, and wherein the... 

4215418 
Integrated digital multiplier circuit using current mode logic
A parallel digital multiplier circuit fabricated in accordance with an advanced triple diffusion process providing feature geometry down to a minimum of two microns and junction depths of less... 

4202039 
Specialized microprocessor for computing the sum of products of two complex operands
A specialized processor capable of computing a sum of products S=Σ±Pi where every product Pi is the product of two nbit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand,... 

4168530 
Multiplication circuit using column compression
A high speed parallel operation, multiplication circuit is provided having a multiplier multiplexor which may function in combination with a column compressor for providing a resultant product,... 

4163287 
Binary multiplier circuit including coding circuit
A binary multiplier circuit wherein the product is expressed in coded form as soon as the linear (or noncoded) product is produced. When a twelvebit binary number is multiplied by another... 

4156922 
Digital system for computation of the values of composite arithmetic expressions
A digital system for computing of the values of composite arithmetic expressions, such as ##EQU1## XIJ WHERE N, K1, K2, ....., KN ARE ARBITRARY INTEGERS, ON NUMBERS XIJ IN A BINARY SYSTEM FOR... 

4153938 
High speed combinatorial digital multiplier
This disclosure relates to a high speed combinatorial 8 by 8 digital multiplier suitable for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth... 

4118785 
Method and apparatus for digital attenuation by pattern shifting
A digital attenuator is disclosed which is capable of having the output PCM signal attenuated nearly in proportion to the input PCM signal level based upon simple logic operations of Pout = α Pin... 

4104729 
Digital multiplier
The digital multiplier is of the add and shift type with a matrix type input in which a number of serial data words can be applied simultaneously to the multiplier enabling the multiplier to... 

4086657 
Fivestage fourbit complex multiplier
A multiplying system for complex numbers using four threestage 4 × 4 bit 2's complement multipliers and a modified adder and subtractor. Two of the 2's complement multipliers are fed to the... 