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5181184 
Apparatus for multiplying realtime 2's complement code in a digital signal processing system and a method for the same
A pipeline multiplier capable of multiplying 2's complement codes is disclosed. The multiplier operates the multiplication faster than the conventional one by receiving a first predeterminedbit... 

5181186 
TPC computers
A triproperty code has been adopted and accordingly combinational and sequential circuits for implementing some arithmetic and logical operations are designed individually then combined into a... 

5173870 
Transmission and latch circuit for logic signal
A latch circuit comprises two inverters having their input terminals connected to their respective output terminals, i.e. crosscoupled to each other. In data writing, two data signals which are... 

5159567 
Programmable serial multiplier
A programmable serial multiplier performing the multiplication of a multiplicand by a fixed constant coded on r bits is formed from a battery of (r/2)1 addition cells (11O 11(r/2)2)... 

5153850 
Method and apparatus for modifying two's complement multiplier to perform unsigned magnitude multiplication
A two's complement multiplier is combined with additional circuit elements and implemented in an integrated circuit to provide a multiplier of selectively operating in two's complement or unsigned... 

5150321 
Apparatus for performing serial binary multiplication
A serial binary multiplier receives a multiplicand and a multiplier, and produces a product. The multiplicand is received in a serial format beginning with a most significant bit and ending with a... 

5146420 
Communicating adder tree system for neural array processor
The neural computing paradigm is characterized as a dynamic and highly computationally intensive system typically consisting of input weight multiplications, product summation, neural state... 

5142490 
Multiplication circuit with storing means
The multiplication circuit is formed in such a manner that the intermediate sums of partial products are divided into a lower places group and a higher places group and the operations for... 

5128890 
Apparatus for performing multiplications with reduced power and a method therefor
An apparatus for performing multiplications with reduced power includes an arithmetic logic unit and a decode block for performing an equivalent of a multiply instruction. A frequentlyencountered... 

5126964 
High performance bitsliced multiplier circuit
An apparatus for performing high performance multiplication in a computer central processor unit which implements a sliced design configuration. Each slice changes its "personality" by virtue of... 

5121431 
Processor method of multiplying large numbers
For a public key encryption system, for example using the RSA algorithm, large numbers, for example each of the order of 256 bits and represented by a plurality of sequentially stored words, must... 

5121352 
Multiplieraccumulator circuit array operable in multiple modes
A highspeed circuit that performs unsigned mode, two's complement mode, and mixed mode multiplicationaccumulation with equal facility. The invention incorporates a high degree of regularity and... 

5117385 
Table lookup multiplier with digital filter
In a digital multiplier for multiplying two multibit binary operands to produce a binary result by means of a lookup table containing all possible products of said operands, reduction of the... 

5113364 
Concurrent stickybit detection and multiplication in a multiplier circuit
An array multiplier calculates a StickyBit concurrently with an iterative multiply operation using a predetermined number of multiplier arrays. An nbit multiplicand operand provides a continuous... 

5095456 
Method for densely packing a complex multiplier
A method for densely packing a complex multiplier for multiplying two complex numbers in the form of (A+jB) and (X+jY) is provided. The complex multiplier consist of two multipliers which perform... 

5095455 
Binary multiplier circuit with improved inputs
A binary multiplier circuit has a logic operator acting as an exclusiveOR gate generating a first intermediate signal which is an exclusiveOR of a first input and a carryin input. An inverter... 

5072419 
Binary tree multiplier constructed of carry save adders having an area efficient floor plan
A binary integer multiplier including a plurality of adder stages, each of such adder stages including a plurality of cells equal to a number of bits in an operand, each of such adder stage... 

5060183 
Parallel multiplier circuit using matrices, including half and full adders
A parallel multiplier utilizing arrays of logic cells. A first circuit logic array forms and sums partial products of the most significant bits of the multiplicand with the multiplier. A second... 

5038315 
Multiplier circuit
In a multiplier for binary numbers represented in two's complement notation, the need to perform signbit extension in order to combine the partial products is avoided by representing the value... 

5031137 
Two input bitserial multiplier
A reduced adder precision apparatus uses two adders to produce a serial output product of two serial input digital numbers. The multiplier operates on a bit by bit basis, beginning with the least... 

5005150 
Digital signal processors
A digital signal processor includes a parallel multiplier having first and second input ports, in which the first input port has conductors for many more bits than does the second input port.... 

5001662 
Method and apparatus for multigauge computation
Methods and apparatus are provided for performing multigauge arithmetic operations in a microprocessor CPU. Special purpose instructions facilitate parallel processing of individual bytes or half... 

4979018 
Semiconductor device with parallel multiplier using at least three wiring layers
In a semiconductor device of the present invention, partial products of a multiplicand and a specific bit of a multiplier are formed by a plurality of partial product producing circuits. The... 

4970675 
Multiplier for binary numbers comprising a very high number of bits
A multiplier for two binary values, X and Y, comprising a very high number (q) of bits, wherein memories storing the numbers X and Y and a result register MR are provided, X being expressed as the... 

4958313 
CMOS parallelserial multiplication circuit and multiplying and adding stages thereof
An integrated CMOS multiplication circuit is operated in a parallelserial mode and executes binary multiplication of a multiplicand and multiplier within the period of a system clock signal by an... 

4947364 
Method in a computing system for performing a multiplication
In a computing system a method for performing a multiplication of a first multiplicand and a second multiplicand is presented. The computing system includes a plurality of registers, an... 

4941121 
Apparatus for high performance multiplication
A method and apparatus for performing high performance multiplication in a computer central processor unit which implements a sliced design configuration. Each slice changes its "personality" by... 

4939687 
Serialparallel multipliers using serial as well as parallel addition of partial products
A cell module which is particularly employable in bitserial silicon compilation methods permits the fabrication and layout of bitserial multipliers having variable word sizes. In particular, the... 

4928259 
Sticky bit predictor for floatingpoint multiplication
In a floatingpoint multiplication of two numbers in which a value of a sticky bit is needed, each of two trailing zero encoders calculates the number of trailing zeroes associated with its... 

4918639 
Overlapped multiplebit scanning multiplication system with banded partial product matrix
A multibit overlapped scanning multiplication system assembles modified partial products in a reduced, nonrectangular banded matrix. The rows of the matrix except for the first and last, are... 

4887233 
Pipeline arithmetic adder and multiplier
A fast pipeline adder comprising a plurality of registered adder rows. In one embodiment, additions in the pipeline are realized in reclocked half adders. In another embodiment, modified adders... 

4868778 
Speed enhancement for multipliers using minimal path algorithm
A binary multiplier architecture which multiplies signed and unsigned operands as unsigned numbers and adds a correction factor which is the two's complement of the other operand if the operand is... 

4866654 
Digital multiplying circuit
A digital multiplying circuit comprises an input terminal serially applied with input vectors which are elements of a finite field GF(2h), where h is a natural number, an output terminal for... 

4860240 
Lowlatency two's complement bitserial multiplier
A double precision, lowlatency two's complement bitserial multiplier operates on the fact that after both inputs have been fully read into the multiplier, the calculation has proceeded to such a... 

4853887 
Binary adder having a fixed operand and parallelserial binary multiplier incorporating such an adder
Binary adder having a fixed operand and a parallelserial binary multiplier incorporating such an adder. The multiplier comprises a dedicated adder, whose elements (transistors, logic gates, etc.)... 

4841468 
Highspeed digital multiplier architecture
A highspeed digital multiplier architecture is implemented in a bipolar very large scale integrated circuit technology. Operand input and product output latches are independently enabled by... 

4839848 
Fast multiplier circuit incorporating parallel arrays of twobit and threebit adders
A multiplier circuit is comprised of multiple arrays of logic cells. Each array has input lines for receiving two multibit binary numbers that are to be multiplied together; and each logic cell... 

4839847 
Nclock, nbitserial multiplier
A bitserial multiplier has a multistage input data register and a multitiered tree of multiplexer/adder circuits coupled thereto which produces, at the output of the adder at the top tier of... 

4831577 
Digital multiplier architecture with triple array summation of partial products
The invention performs the multiplication and/or accumulation of digital numbers in either two's complement of unsigned magnitude representation. A modified Booth algorithm minimizes the number of... 

4829585 
Electronic image processing circuit
An apparatus and method for high speed parallel processing of image data corresponding to picture elements of an image in which the image data for each picture element is formatted as a binary... 

4825401 
Functional dividable multiplier array circuit for multiplication of full words or simultaneous multiplication of two half words
A multiplier array circuit including decoders for decoding a multiplier on the basis of Booth's algorithm; cell array blocks for receiving the selection signals from the decoders and a... 

4823300 
Performing binary multiplication using minimal path algorithm
A binary multiplier architecture which performs two's complement multiplication when the multiplier has 1's in more than half of its bits and performs unsigned binary multiplication by adding only... 

4809211 
High speed parallel binary multiplier
An n×n bit multiplier of a type having input and output registers and associated multiplexers, a multiplier array and adders, a shifter and an accumulator. The multiplier includes a temporary... 

4809212 
High throughput extendedprecision multiplier
A multiplier formed as a single integrated circuit chip generates in consecutive clock cycles the singleprecision partial products of multipleprecision operands. Provision of an onchip... 

4800517 
Wordsliced signal processor
Method and apparatus for processing digital signals represented as binary words, employing a portion of each word (a "slice") to afford appropriate accuracy. Particularly suited to medium to... 

4791600 
Digital pipelined heterodyne circuit
A digital pipelined heterodyne circuit includes sine and cosine function generators for generating mbit digital coefficients and an mstage digital multiplier for multiplying the coefficients by... 

4761756 
Signed multiplier with three port adder and automatic adjustment for signed operands
Disclosed is a signed multiplier for use in a data processing system that handles 2's complement operands. The signed multiplier operates to form a preliminary product independently of the signs... 

4754421 
Multiple precision multiplication device
A multiple precision multiplication device includes accumulators coupled to the output of an array multiplier. The accumulators store partial products which are then added back into partial... 

4752905 
Highspeed multiplier having carrysave adder circuit
A highspeed multiplier adapted to VLSI with a regularly arranged structure having a reduced number of addition stages. There is provided a carry save adder circuit wherein a time difference is... 

4750144 
Real time pipelined system for forming the sum of products in the processing of video data
A 3by3 convolver utilizes 9 binary arithmetic units (10) connected in cascade for multiplying 12bit binary pixel values pi which are positive or two's complement binary numbers by 5bit... 