Matches 151 - 200 out of 335 < 1 2 3 4 5 6 7 >


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5615141 Multiplying apparatus  
A multiplying apparatus, capable of processing in relatively high speed with relatively small hardware quantity, in which the circuits for relative-digits are composed of adders 1a, 1b, 1c, 1d,...
5606677 Packed word pair multiply operation forming output including most significant bits of product and other bits of one input  
This invention is a method and apparatus for multiplication which enables two factors to be packed into the same size data word as the product. The invention partitions two N bit buses (210, 202)...
5602767 Galois field polynomial multiply/divide circuit and a digital signal processor incorporating same  
The multiply/divide circuit uses an exclusive OR function of an ALU in a DSP. The result of the exclusive OR function through accumulators and shift registers which recycle the shifted signals...
5600569 Method, system, and apparatus for automatically designing logic circuit, and multiplier  
With respect to each bit of a multiplier factor, it is judged whether or not the multiplier factor is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not...
5594912 Digital signal processing device with optimized ALU circuit and logic block for controlling one of two registers based on the contents of the multiplication register  
A digital signal processing device includes at least one peripheral unit, a data bus and at least three data registers and a flag register exchanging binary-encoded data with the at least one...
5586070 Structure and method for embedding two small multipliers in a larger multiplier  
A multiplier circuit which performs selectable multiplication operations on a first word having an upper byte and a lower byte and a second word having an upper byte and a lower byte. A first...
5586069 Arithmetic logic unit with zero sum prediction  
An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition...
5583804 Data processing using multiply-accumulate instructions  
A data processing system is described utilizes a multiplier-accumulator 108 that performs both a first class of multiply-accumulate instructions and a second class of multiply-accumulate...
5579253 Computer multiply instruction with a subresult selection option  
A N-bit by N-bit multiplication apparatus having the ability to select a part of the multiplication result for storage into a result register N-bits wide. A first embodiment of the invention...
5576982 Fast significant bit calculator and its application to integer multiplication and division  
Disclosed is a Significant Bit Calculator (SBC) for determining the number of significant bits or nibbles of an operand in one clock period, and for using the result in performing binary...
5553010 Data shifting circuit capable of an original data width rotation and a double data width rotation  
A data shifting circuit comprises a barrel shifter for shifting by a plurality of bits data having a width twice that of a certain data width, and a data controller for supplying the same data...
5539685 Multiplier device with overflow detection function  
A multiplier device with an overflow detection function includes a multiplier register, a multiplicand register, a priority encoder, a shifter for shifting the output from the multiplicand...
5524090 Apparatus for multiplying long integers  
A multiplier apparatus designed to multiply integers of many figures with a small circuit scale in such a manner that an input value is partitioned and multiplication is performed by taking...
5511018 Multiplier, especially a serial bit multiplier, free from internal overflow, and method for preventing internal overflow in a multiplier  
A multiplier for least significant bit first multiplication of a multiplicand coded on n bits by a multiplier coefficient includes a processor which, for each bit of the decimal part of the...
5497342 Cellular multiplier comprising a tree of the overturned stairs type, and method of implementation  
A multiplier of order p and of depth n+1 is formed by a root R constituted by a carry-save adder and by a multiplier body CO(p,n) of order p and of depth n formed by a five-input connector...
5495346 Element generator for dither matrix and a dithering apparatus using the same  
An element generator for a dither matrix comprises a logic device which receives a row address and a column address and performs a logic operation thereon so as to produce a dither element...
5491653 Differential carry-save adder and multiplier  
A Carry-Save Adder circuit having differential signal response and output is provided. The circuit includes a pair of cross-coupled transistors powered by an upper voltage rail. The output of a...
5490101 Digital data multiplying circuit  
A digital data multiplying circuit has a double clock alternating sampler for alternately sampling the digital data applied from a plurality of input buses by a time-division system in accordance...
5483477 Multiplying circuit and microcomputer including the same  
A multiplying circuit wherein an adder 7 outputs a value "0" in which both of a positive part and a negative part of a number with a redundant code are "1", and at a last cycle of the...
5467296 High-speed small digital multiplier  
A digital multiplier absolutizes a multiplicand and a multiplier for decreasing component bits thereof, and multiplies the absolutized multiplicand by the absolutized multiplier for producing a...
5465226 High speed digital parallel multiplier  
A plurality of multiplicand bit transmission lines and a plurality of multiplier bit transmission lines or their decoding signal transmission lines are arranged in a two-dimensional plane, and...
5457646 Partial carry-save pipeline multiplier  
A pipeline multiplier is used for multiplying a multiplicand to a multiplier. The pipeline multiplier includes a plurality of adder stages each adder stage includes a partial product processor for...
5442579 Combined multiplier and accumulator  
A method for summing a sequence of binary product terms utilizing a modified Booth's algorithm in an arithmetic unit, wherein the arithmetic unit has a multiplicand register, a multiplier...
5436860 Combined multiplier/shifter and method therefor  
A combined multiplier/shifter (150) uses an existing high-speed multiplier to perform both multiplies and programmable left and right shifts without a dedicated high-speed shifter. A shift decoder...
5424971 Unsigned constant multiplier compiler  
A constant multiplier compiler model allows a constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a constant multiplier circuit for...
5422805 Method and apparatus for multiplying two numbers using signed arithmetic  
A signed arithmetic data processing system (20) detects a multiply (MUL) or a multiply-and-accumulate (MAC) instruction in which a multiplier and a multiplicand each assume their respective...
5420815 Digital multiplication and accumulation system  
A multiplication system performs a series of multiplications and accumulations of plural pairs of first and second operands. The system includes first and second buses, a memory for storing the...
5412591 Schematic compiler for a multi-format high speed multiplier  
A multiplier compiler produces a schematic of a high-speed, multi-format multiplier. The compiler receives user information which indicates design preferences. Based on the user information the...
5404323 Pipelined multiplier for signed multiplication  
A pipelined multiplier for signed multiplication has a plurality of pipeline stages, each of which includes a row of registers, and a row of operating cells. The operating cells includes a...
5402369 Method and apparatus for digital multiplication based on sums and differences of finite sets of powers of two  
A method and apparatus is disclosed for digital multiplication based on sums and differences of finite sets of powers of two. It is observed that for a given multiplicand signal A, multiples of...
5400272 Diagonal propagation digital multiplier  
A diagonal propagation, digital multiplier of a kind adapted to multiply a first factor by a second factor, with the factors each being expressed as a binary number including a non-volatile memory...
5351206 Signed two's complement constant multiplier compiler  
A constant multiplier compiler model allows a signed two's complement constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a signed...
5347481 Method and apparatus for multiplying denormalized binary floating point numbers without additional delay  
A structure of logic gates, partial product circuits, and a multiplier tree is described for multiplying of two operands which may contain denormalized numbers in the same amount of time as needed...
5347482 Multiplier tree using nine-to-three adders  
A multiplier tree sums the partial products of a multiplication operation, employing a regular hierarchical arrangement of bit adders that accept nine initial inputs and a carry input and produce...
5343416 Method and apparatus for re-configuring a partial product reduction tree  
An apparatus is described for re-configuring a partial product reduction tree. The partial product reduction tree contains carry-save-adders and is represented by a plurality of rectangles and...
5327368 Chunky binary multiplier and method of operation  
A fast binary reduction tree of the type used in high speed digital computer multiplication circuits is disclosed having chunky adders formed by sub-dividing carry propagate adders into chunks of...
5313414 Canonical signed two's complement constant multiplier compiler  
A constant multiplier compiler model allows a modified canonical signed two's complement constant multiplier circuit design to be generated from a user specification of the desired constant. A...
5309384 Digital multiplier with carry-sum input  
A digital multiplier that includes a combinatorial ripple carry adder for adding the sum and carry components of a first operand represented in sum and carry form to produce a converted first...
5285405 Inner product calculating circuit  
An inner product calculating circuit for executing a calculation of an inner product on the basis of one or more vector data and one or more coefficients. The circuit comprises a selective...
5283755 Multiplier employing carry select or carry look-ahead adders in hierarchical tree configuration  
A multiplication circuit for a floating point digital processing system includes a partial products generator and a carry adder circuit for determining a product resulting from multiplication of...
5265043 Wallace tree multiplier array having an improved layout topology  
A Wallace tree multiplier array (40) performs multiply operations using operands received via a data path (42) having a predetermined height. Rows of carry save adders (CSAs 15'-19") add sets of...
5262975 Serial input multiplier apparatus  
A serial-input-output multiplying circuit includes AND gates for providing partial products of an input number and a coefficient, a plurality of full adders supplied at input portions thereof with...
5255216 Reduced hardware look up table multiplier  
A method and apparatus for multiplying an N bit number X(t) by an M bit number O, and a method for making such an apparatus for multiplying numbers are described. The N bit number is partitioned...
5253194 Digital multiplier  
A decode circuit decodes digital signals X1 and X0 as multiplicand to output decoded signals A0-A3. One of these decoded signals A3-A0 is set to be logic 1 in accordance with a value of a...
5245564 Apparatus for multiplying operands  
In an apparatus and method for computing inverses and square roots a highly accurate initial approximation is computed using a second order polynomial equation, the coefficients of which are...
5243552 Coefficient multiplying circuit  
A coefficient multiplying circuit comprises (m+1) bit shifters which are supplied with an input binary signal and respectively have a number of bit shifts different from one another in association...
5231601 Digital multiplier based upon a regularly structured sum of products adder array for partial product reduction  
A digital multiplier is configured from a number of identical circuit "slices" with interconnecting signals arranged such that the need for large wiring channels is eliminated. The resulting...
5220524 Machine method to perform newton iterations for reciprocals  
The machine method of the present embodiment relates to iterative numerical techniques adapted for use in digital circuitry, such as floating point multipliers and floating point adder-subtractor...
5206823 Apparatus to perform Newton iterations for reciprocal and reciprocal square root  
The apparatus of the present embodiment relates to iterative numerical techniques adapted for use in digital circuitry, such as floating point multipliers and floating point adder-subtractor...
5181183 Discrete cosine transform circuit suitable for integrated circuit implementation  
A discrete cosine transform (DCT) circuit providing DCT and inverse DCT results, receiving N input data and a selection signal, includes a first switch for selecting input data or accumulation...

Matches 151 - 200 out of 335 < 1 2 3 4 5 6 7 >