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6370559 Method and apparatus for performing N bit by 2*N−1 bit signed multiplications  
A method and apparatus for performing N bit by 2*N (or 2*N−1) bit signed multiplication using two N bit multiply instructions. According to one aspect of the invention, a method for performing...
6347326 N bit by M bit multiplication of twos complement numbers using N/2&plus 1 X M/2&plus 1 bit multipliers  
The operands of an N×M bit multiplication are partitioned into N/j+1 and M/k+1 bit signed submultiples. The most significant submultiple is assigned the sign of the operand, while each of the less...
6330631 Data alignment between buses  
A bus bridge for a computer system for bridging first and second buses includes a shift and accumulate unit. The shift and accumulate unit includes a shifter having an input connected to receive...
6311203 Multiplier, and fixed coefficient FIR digital filter having plural multipliers  
A multiplication device for performing a multiplication operation on a multiplicand X and two fixed coefficients C1 and C2 where C1>C2. The multiplication device comprises a multiplier for...
6298369 High speed multiplier  
The high speed multiplier takes advantage of results from previous calculations by recognizing that in many cases the multiplicand between a first and second multiplication differs only slightly....
6286023 Partitioned adder tree supported by a multiplexer configuration  
An adder tree is partitioned into two parts. One multiplexer provides a first bit group to the first part of the tree. A second multiplexer provides a second bit group to the second part of the...
6286024 High-efficiency multiplier and multiplying method  
Upon execution of four sets of m/2 bit×n/2 bit multiplication, four multiplicand selectors select m/2-bit multiplicands respectively and four multiplicator selectors select corresponding n/2-bit...
6233597 Computing apparatus for double-precision multiplication  
In a binary fixed-point number system in which the most significant bit is a sign bit and the decimal point is between the most significant bit and a bit which is lower by one bit than the most...
6202077 SIMD data processing extended precision arithmetic operand format  
Two related extended precision operand formats provide for efficient multiply/accumulate operations in a SIMD data processing system. Each format utilizes a group of "b" bit elements in a vector...
6181983 Method of command control for a robot manipulator  
Beginning with a successive commanded end-effector destination shift, the method of the invention, which includes a calculation corresponding to a special algorithm of inverse kinematics using the...
6148319 Multiplier  
There is disclosed a multiplier having a digit rounding function which operates by selecting an added value for rounding a digit in the process of adding partial products, thereby reducing a...
6125379 Parallel VLSI shift switch logic devices  
A new logic with shift switches incorporating novel parallel compressors and counters called C4 and (7,3) families. This shift switch logic deals with modulo arithmetic operations. It employs a...
6115732 Method and apparatus for compressing intermediate products  
A processor capable of efficiently performing iterative calculations is disclosed. The processor comprises a multiplier that is configured to perform iterative multiplication operations to...
6078941 Computational structure having multiple stages wherein each stage includes a pair of adders and a multiplexing circuit capable of operating in parallel  
A modular computational structure includes a pipeline having first and second adder stages. Each adder stage includes a pair of adders which operate in parallel, and outputs ports of the first...
6066178 Automated design method and system for synthesizing digital multipliers  
A computer-based method and system is disclosed that automates the design and layout of digital multiplier circuits. The preferred method utilizes an automatic design generator having a user...
6065033 Wallace-tree multipliers using half and full adders  
An apparatus sums a plurality of columns of binary bits to produce a plurality of partial sum and carry bits. The bits of a particular column being of the same order of magnitude, and the bits of...
6029187 Fast regular multiplier architecture  
A multiplier architecture in accordance with the present invention provides increased operating speed, and yet maintains regularity in its structure in order to achieve a small floor plan when...
5991789 Circuit arrangement for realizing logic elements that can be represented by threshold value equations  
In a circuit arrangement wherein all logic elements can be represented in the form of a threshold value equation, for this purpose, transistors connected in parallel of a transistor unit are...
5982314 Self-timed multiplier for gain compensation and reduced latency in analog to digital converters  
A self-timed multiplier and method are disclosed together with an analog to digital converter (ADC), which reduces ADC latency without requiring large silicon areas for implementation. The...
5974437 Fast array multiplier  
A number of adder structures (also referred to herein as "tiles" and "Quickadders™") are provided which may be constructed with positively and/or negatively weighted and signed inputs and outputs...
5954791 Multipliers with a shorter run time  
A multiplication circuit for binary coded numbers uses rows of adders and multipliers for parallel computation. Sign bit supplementation is used in which sign bits are supplemented by binary...
5956264 Circuit arrangement for digital multiplication of integers  
A circuit arrangement for digital multiplication of integers, having an encoding unit, an adding unit, which adds the output values of the encoding unit, and a decoding unit, which decodes the...
5956265 Boolean digital multiplier  
A boolean multiplier is disclosed. The boolean multiplier includes a plurality of input buffers for storing a first operand and a second operand. The multiplier also includes a first set of gates...
5944776 Fast carry-sum form booth encoder  
A fast carry-sum form Booth encoder is used in a multiplicative divider to iteratively multiply one number by a series of numbers to produce the result of a divide or square root operation. The...
5943250 Parallel multiplier that supports multiple numbers with different bit lengths  
A parallel multiplier for multiplying a multiplicand and multiplier with large bit lengths as well as simultaneously multiplying several multiplicands and multipliers with smaller bit lengths is...
5935197 Data processing circuit and method of operation performing arithmetic processing on data signals  
The present invention provides a data processing circuit and method for performing arithmetic processing on data signals input to the circuit, comprising: a plurality of input terminals for...
5920497 Method and apparatus for performing a double precision operation using a single instruction type  
The present invention relates to a method and apparatus for performing double precision operations using a single type of instruction, wherein a shift bit in a status register is cleared...
5898604 Digital Signal Processor employing a random-access memory and method for performing multiplication  
The invention relates to a digital signal processor with a RAM (random-access memory) having its output connected to a first input and, through a first temporary storage device to a second input...
5880985 Efficient combined array for 2n bit n bit multiplications  
In order to multiply operands of different binary lengths using a common combined array, for example to do both 8 bit by 8 bit and 16 bit by 16 bit multiplications, 2m-1 multiplications are...
5841684 Method and apparatus for computer implemented constant multiplication with multipliers having repeated patterns including shifting of replicas and patterns having at least two digit positions with non-zero values  
A method for designing a constant multiplier system comprises identifying a repeated pattern in a minimal signed digit expression of a multiplier, designing a first accumulator stage to compute...
5835393 Integrated pre-adder for a multiplier  
A preadder for a multiplier integrates a pre-adder and Booth encoder. The integrated pre-adder/Booth encoder comprises multiple stages, each of which adds and encodes multiple bits (usually two)...
5808927 Apparatus for performing two's complement and unsigned multiply accumulate  
A parallel multiply accumulator that provides a two's complement and unsigned multiply has a accumulator structure that minimizes the local and global interconnect lengths so that the design...
5790446 Floating point multiplier with reduced critical paths using delay matching techniques  
A floating point multiplier with partial support for subnormal operands and results uses radix-4 or modified Booth encoding and a binary tree of 4:2 compressors to generate the 53×53...
5787031 Divider and multiplier/divider using said divider  
A divider constituted by connecting in series a plurality of arithmetic units in such a manner as to correspond to the number of bits of first data, said divider comprising: a divisor data input...
5787029 Ultra low power multiplier  
A multiplier using a modified Booth algorithm dissipates power proportional to the magnitude of one of the operands, and logic races are eliminated using iterative networks.
5777907 Processor for selectively performing multiplication/division  
A processor 10 for selectively performing multiplication or division of two inputs comprises a pre-processing unit 20 for modifying the signs of the inputs; an aligning unit 30 for aligning bit...
5771186 System and method for multiplying in a data processing system  
A multiplier circuit within a CPU has its selections of partial products reordered in a unique manner so that shift left capabilities are eliminated and the hardware is required to only perform...
5764558 Method and system for efficiently multiplying signed and unsigned variable width operands  
A plurality of multipliers for multiplying numbers having B number of bits are provided for multiplying A-operands having B number of bits by a B-operand having B number of bits. Pairs of A- and...
5751622 Structure and method for signed multiplication using large multiplier having two embedded signed multipliers  
A signed multiplier circuit which performs selectable multiplication operations on a first word having an upper byte and a lower byte and a second word having an upper byte and a lower byte. A...
5737257 Method and apparatus for compression of integer multiplication table  
A method of compressing an integer multiplication table including the steps of first eliminating one of the two symmetrical and identical sections in the table, eliminating the products of 0...
5734600 Polynomial multiplier apparatus and method  
A multiplier efficiently multiplies signed or unsigned binary polynomial operands. The multiplier includes storage means for temporary storage of a current multiplier and a current multiplicand...
5715187 Method and apparatus for integer multiplication  
A binary multiplication method utilizing a combined table lookup and long multiplication to simplify the multiplication procedure, to improve the computational speed, and to save half of the...
5691930 Booth encoder in a binary multiplier  
A partial product generator in a binary multiplier for multiplying a parallel n-bit binary multiplier and a parallel m-bit binary multiplicand comprises n/2 (n being an even integer) or (n+1)/2 (n...
5684730 Booth multiplier for trigonometric functions  
Circuit for multiplying data in accordance with a Booth algorithm, in which the coding of the control signals is adapted to the characteristics of symmetry of a trigonometric function. The values...
5666301 Multiplier carrying out numeric calculation at high speed  
Luminance value data including data of R, G, and B and data α representing transparency, each of 8 bits, and a coefficient expressed by floating-point data are directly applied to an operation...
5661673 Power efficient booth multiplier using clock gating  
A multiplier which uses Booth recoding to multiply large word length operands. The multiplier can be divided into three functional modules: 1) operand loading module, 2) Booth partial product...
5642306 Method and apparatus for a single instruction multiple data early-out zero-skip multiplier  
A method and apparatus for multiple parallel multiplications of multiple packed data using a single multiplier is provided. Given multiple packed data as multiplicand blocks and as multiplier...
5623683 Two stage binary multiplier  
The present invention provides a method and apparatus for achieving m-bit×m-bit multiplication in two states with a minimum amount of hardware. The invention multiplies an m-bit multiplicand A by...
5623434 Structure and method of using an arithmetic and logic unit for carry propagation stage of a multiplier  
A multiplier circuit for use in a system which includes an arithmetic and logic unit (ALU). The multiplier circuit includes a carry save stage which receives a first data value and a second data...
5617346 Multiplication device using semiconductor memory  
The present invention discloses a multiplication device. A multiplicand X of eight bits and a multiplier Y of eight bits are input and a product P of sixteen bits is found from these...

Matches 101 - 150 out of 335 < 1 2 3 4 5 6 7 >