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7565391 Binary digit multiplications and applications  
A multiplying system for binary digits. The digits are multiplied in a rectangular memory array, where the digits are placed along the edges, and intersections between 1's form blocks of 1's in...
7506017 Verifiable multimode multipliers  
A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex...
7490121 Modular binary multiplier for signed and unsigned operands of variable widths  
A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a...
7477171 Binary-to-BCD conversion  
Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.
7447726 Polynomial and integer multiplication  
A method and apparatus for generating a plurality of concurrent significant bits forming at least a portion of a product from at least two partial products, the method comprising the following...
7401109 Multiplication of multi-precision numbers having a size of a power of two  
Multi-precision multiplication methods include storing a first operand and a second operand as a first array and a second array of n words. A first weighted sum is determined from multiple...
7392276 Efficient multiplication sequence for large integer operands wider than the multiplier hardware  
A method of operating a multiplication circuit to perform multiply-accumulate operations on multi-word operands is characterized by an operations sequencer that is programmed to direct the...
7389317 Long instruction word controlling plural independent processor operations  
A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first...
7356554 Variable fixed multipliers using memory blocks  
A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift...
7346644 Devices and methods with programmable logic and digital signal processing regions  
A programmable logic integrated circuit device (“PLD”) includes programmable logic and a dedicated (i.e., at least partly hard-wired) digital signal processing region for performing or at least...
7318080 Split radix multiplication  
A first number is multiplied by a second number, by representing the first number as a first set of one or more W-bit wide numbers, and representing the second number as a second set of one or...
7315163 Arithmetic unit  
In order to correct an overflow of a multiplication result while improving the operation speed, an overflow detection unit detects an overflow based on whether a multiplicand A and a multiplier B...
7296049 Fast multiplication circuits  
Fast multiplication of two operands may be achieved by an interstitial product generator that generates an interstitial product from each of a plurality of mult-ibit segments of a multiplier....
7269616 Transitive processing unit for performing complex operations  
The present invention provides a circuit for a programmable transitive processing unit for performing complex functions, such as multiplication, pipelining of one or more values, and/or shift...
7269617 Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry  
A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers...
7191203 Method and system for high-speed multiplication  
A system, method, and computer product for high-speed multiplication of binary numbers. A multiplier X is first encoded, and the encoded multiplier is then used in a multiplication process that...
7167890 Multiplier-based processor-in-memory architectures for image and graphics processing  
A Procesor-In-Memory (PIM) includes a digital accelerator for image and graphics processing. The digital accelerator is based on an ALU having multipliers for processing combinations of bits...
7139787 Multiply execution unit for performing integer and XOR multiplication  
A multiply execution unit that is operable to generate the integer product and the XOR product of a multiplicand and a multiplier. The multiply execution unit includes a summing circuit for...
7080115 Low-error canonic-signed-digit fixed-width multiplier, and method for designing same  
An error compensation bias circuit and method for a canonic signed digit (CSD) fixed-width multiplier that receives a W-bit input and produces a W-bit product. Truncated bits of the multiplier are...
7069290 Power efficient booth recoded multiplier and method of multiplication  
In the multiplier, a partial product circuit generates a partial product based on a multiplicand operand and outputs of a Booth recoder circuit, which operates on a multiplier operand. The partial...
7047271 DSP execution unit for efficient alternate modes for processing multiple data sizes  
In one embodiment, a digital signal processor (DSP) processes both n-bit data and (n/2)-bit data. The DSP includes multiple processing paths. A first processing path processes n-bit data. A second...
7028068 Alternate phase dual compression-tree multiplier  
A multiplier includes a plurality of subunits. Each of the plurality of subunits is configured to perform a portion of a multiplication operation, and the plurality of subunits are coupled...
7024444 Split multiplier array and method of operation  
There is disclosed a multiplier circuit for use in a data processor. The multiplier circuit comprises a partial products generating circuit that receives a multiplicand value and a multiplier...
6981013 Low power, minimal area tap multiplier  
A low power tap multiplier multiplies a m-bit multiplier and a n-bit multiplicand to output a p-bit multiplication product. The p-bit product is one bit more than the n-bit multiplicand when the...
6959316 Dynamically configurable processor  
A data processor, such as a DSP, includes a multiplier block having a multiplier front end for generating partial products from input operands, and further includes a plurality of ALUs having...
6952711 Maximally negative signed fractional number multiplication  
A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a...
6917218 Serial finite field multiplier  
The present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit, thereby minimizing power consumption and circuit area in implementing the finite...
6915322 Multiplier capable of multiplication of large multiplicands and parallel multiplications of small multiplicands  
A multiply unit uses four multipliers independently to perform for four parallel multiplications of single-width operands or uses the four multiplier cooperatively with an adder to perform a...
6772186 Multimedia multiply-adder  
A multimedia processor is capable of concurrently carrying out processing tasks at different degrees of precision suitable for a variety of purposes and displays high performance of consecutively...
6745319 Microprocessor with instructions for shuffling and dealing data  
A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected...
6742011 Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry  
The present invention generally relates to an apparatus and method for efficiently summing the partial product bits produced by a multiplier. Briefly described, in architecture, the apparatus...
6742012 Apparatus and method for performing multiplication operations  
The present invention provides an apparatus and method for processing data using a multiplying circuit for performing a multiplication of a W/2 bit data value by a W bit data value. An instruction...
6731138 Circuits and methods for selectively latching the output of an adder  
Methods and circuits for selectively latching the output of an adder are disclosed. One such circuit includes first and second NAND gates, each of which has an input coupled to a clock signal. The...
6728744 Wide word multiplier using booth encoding  
A multiplier for computing a final product of a first operand and a second operand comprising a multiplier array for forming a product of the first operand and second operand in carry-save form; a...
6711602 Data processor with flexible multiply unit  
An embodiment of the invention includes a pair of parallel 16×16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for...
6708193 Linear summation multiplier array implementation for both signed and unsigned multiplication  
A system and method are disclosed which provide a multiplier comprising a linear summation array that is implemented in a manner that enables both signed and unsigned multiplication to be...
6704762 Multiplier and arithmetic unit for calculating sum of product  
In a case of performing a multiplication operation with low accuracy, a value of the most significant bit included in the least significant half the bits of a multiplier is replaced with “0”. A...
6687726 Apparatus for multiplication by constant factors for video compression method (MPEG)  
Particularly with relatively complex multiplication devices with a downstream shift device, such as those which occur in video compression devices, the apparatus is used to save chip area and to...
6684236 System of and method for efficiently performing computations through extended booth encoding of the operands thereto  
A system of and method for extended Booth encoding of two binary numbers, K and L. A stage of the encoder receives K[2n+1], K[2n], L[2n+1], and C[n−1], N−1≧n≧0, with N being the length of L, and...
RE38387 Multiplier circuit for multiplication operation between binary and twos complement numbers  
A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are...
6523055 Circuit and method for multiplying and accumulating the sum of two products in a single cycle  
A multiplication accumulation circuit (abbreviated as “MAC”) has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the...
6516334 Circuit arrangement with combinatorial blocks arranged between registers  
In the circuit arrangement, combinatorial blocks are arranged between an input register (RG1) and an output register (RG2). The output of the input register (before the combinatorial blocks (KBL))...
6484194 Low cost multiplier block with chain capability  
This application describes a method of multiplying numbers represented in multiple-word chains. The multiplication scheme allows for the multiplication of both signed and unsigned numbers of...
6483343 Configurable computational unit embedded in a programmable device  
A plurality of configurable computational units are embedded in a programmable device, such as a field programmable gate array. Each configurable computational unit includes an adder circuit that...
6484193 Fully pipelined parallel multiplier with a fast clock cycle  
A fully pipelined parallel multiplier with a fast clock cycle. The pipelined parallel multiplier contains three units: a bit-product matrix unit, a reduction unit, and an addition unit. The...
6460064 Multiplier for operating n bits and n/2 bits and method therefor  
A multiplier for multiplying n bits and n/2 bits is disclosed, wherein a word multiplication is implemented by input of two words. The apparatus includes an encoder receiving the two words and...
6460065 Circuit and method for partial product bit shifting  
A circuit for shifting the number of partial product bits per column in an adder tree is provided. A partial product bit is generated having a weight 22k that has a 1 value only if one input bit...
6434584 Flexible accumulator register file for use in high performance microprocessors  
Specialized microprocessor hardware 10 and a specialized instruction set that provides efficient data processing operations on long word length or bit length data. Instructions that manipulate...
6434586 Narrow Wallace multiplier  
A multiplier including a processor that generates at least one N by M array of partial products. The processor includes a first section that performs a first operation that generates an N by M...
6421699 Method and system for a speedup of a bit multiplier  
A method and system is provided which overlaps the process of partial product reduction and the final adder in both higher- and lower-order bits when performing multiplication. The method and...

Matches 51 - 100 out of 335 < 1 2 3 4 5 6 7 >