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7620677 |
4:2 Carry save adder and 4:2 carry save adding method
Provided are a simplified 4:2 carry save adder (CSA) cell and a 4:2 carry save adding method. The 4:2 CSA cell is formed of an odd detector and first through sixth switches through logic...
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7595659 |
Logic cell array and bus system
A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for...
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7587443 |
Digital signal processor with efficient multi-modal multiplier
A digital signal processor architecture allows the digital signal processor to be used efficiently for multiplying words which are longer than the word length for which the architecture is...
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7565391 |
Binary digit multiplications and applications
A multiplying system for binary digits. The digits are multiplied in a rectangular memory array, where the digits are placed along the edges, and intersections between 1's form blocks of 1's in the...
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7564971 |
Apparatus and method for performing Montgomery type modular multiplication
A signal processing apparatus for performing modular multiplication for use in a signal processing system includes a first logic for outputting a signed multiplicand by selectively performing a...
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7562106 |
Multi-value digital calculating circuits, including multipliers
Apparatus and method for performing multi-value arithmetic operations are disclosed. Multi-value signals can be added, subtracted and multiplied using a first truth table to generate a residue and...
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7539714 |
Method, apparatus, and instruction for performing a sign operation that multiplies
Method, apparatus, and program means for performing a sign and multiply operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the...
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7519646 |
Reconfigurable SIMD vector processing system
A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant...
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7519643 |
Montgomery multiplier for RSA security module
A Montgomery multiplier for providing security of information used in smart cards from hacking by a differential power analysis attack by minimizing power consumption difference by the input data....
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7506017 |
Verifiable multimode multipliers
A verifiable duplex multiplier circuit is provided. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex...
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7506016 |
Multiplier device
Multiplier device comprising first to n th multipliers M 1 to M n for multiplying a carrier modulated information signal with first to n th mutually phase shifted and identical, substantially...
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7487196 |
Methods and apparatus for implementing a saturating multiplier
Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating....
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7418468 |
Low-voltage CMOS circuits for analog decoders
Low-voltage CMOS (Complementary Metal Oxide Semiconductor) circuits, suitable for analog decoders, for example, are provided. The circuits include multiplier modules that receive first input...
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7395300 |
System, and method for calculating product of constant and mixed number power of two
Presented herein are systems and methods for computing the product of a constant and a mixed number power of two. A circuit comprises a first register, a second register, a memory, a third...
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7395299 |
System and method for efficient hardware implementation of a perfect precision blending function
An apparatus and method for efficiently calculating an intermediate value between a first end value such that the area and time required to implement this operation is minimized is described. The...
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7389317 |
Long instruction word controlling plural independent processor operations
A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first...
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7266579 |
Combined polynomial and natural multiplier architecture
Integrated circuit parallel multiplication circuits, including multipliers that deliver natural multiplication products and multipliers that deliver polynomial products with coefficients over...
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7240204 |
Scalable and unified multiplication methods and apparatus
Scalable and unified multipliers for multiplication of cryptographic parameters represented as elements of either of the prime field (GF(p)) and the binary extension field (GF(2 m )) include...
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7213043 |
Sparce-redundant fixed point arithmetic modules
A fixed-point arithmetic unit comprises a plurality of full-adders and half-adders arranged in at least an input row and an output row. A plurality of inputs to the input row is arranged to receive...
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7212959 |
Method and apparatus for accumulating floating point values
A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained....
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7206801 |
Digital multiplier with reduced spurious switching by means of Latch Adders
A digital Parallel Multiplier has a Partial Product Generator, a First Stage Adder Circuit and a Final Stage Adder Circuit. The spurious switching in the First Stage Adder Circuit may be...
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7200194 |
Receiver signal dynamic range compensation based on received signal strength indicator
A method for processing a received signal at a mobile receiver of a wireless communications system is disclosed. The method comprises demodulating the received signal to obtain an analog base band...
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7194498 |
Higher radix multiplier with simplified partial product generator
A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a...
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7177894 |
Switching activity reduced coding for low-power digital signal processing circuitry
A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a...
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7159004 |
Adder, multiplier and integrated circuit
An adder includes a first XOR element for generating an XOR output of the first and the second data inputs, a first multiplexer for selecting one of the first carry input or the first data input...
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7080114 |
High speed scaleable multiplier
A high speed scalable multiplier. The high speed scalable multiplier can include a folding multiplier configured to fold multiplicands and multipliers where individual ones of the multiplicands and...
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7062526 |
Microprocessor with rounding multiply instructions
A functional unit in a digital system is provided with a rounding Multiplication instruction, wherein a most significant product of first pair of elements is combined with a least significant...
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7024444 |
Split multiplier array and method of operation
There is disclosed a multiplier circuit for use in a data processor. The multiplier circuit comprises a partial products generating circuit that receives a multiplicand value and a multiplier value...
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6993551 |
Sparse-coefficient functions for reducing computational requirements
A method for reducing computational steps in a digital processor including multiplications producing a plurality of multiplication products. This method specifies a desired multiplication function...
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6993550 |
Fixed point multiplying apparatus and method using encoded multiplicand
The invention relates to a fixed point multiplying apparatus and method using an encoded multiplicand. The multiplicand is encoded into an independent binary system instead of a conventional binary...
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6993071 |
Low-cost high-speed multiplier/accumulator unit for decision feedback equalizers
A multiplier device for multiplying one of a discrete set of digital level values with a filter coefficient in a filter device implemented in a decision feedback equalizer including (i) a decoder...
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6959316 |
Dynamically configurable processor
A data processor, such as a DSP, includes a multiplier block having a multiplier front end for generating partial products from input operands, and further includes a plurality of ALUs having...
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6950840 |
Noise invariant circuits, systems and methods
The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a...
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6940920 |
Multiplier arrangement, signal modulator and transmitter
A multiplier arrangement (MUXER) is adapted to generate from analog phase information and from high-frequency local oscillator signals, components of a high-frequency phase vector (PV), and to...
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6934728 |
Euclidean distance instructions
A method and processor for multiplication operation instruction processing are provided. Multiplication operation instructions are executed on source operands in data memory locations. The...
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6922717 |
Method and apparatus for performing modular multiplication
A method and apparatus for performing modular multiplication is disclosed. An apparatus in accordance with one embodiment of the present invention includes a modular multiplier including a...
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6915322 |
Multiplier capable of multiplication of large multiplicands and parallel multiplications of small multiplicands
A multiply unit uses four multipliers independently to perform for four parallel multiplications of single-width operands or uses the four multiplier cooperatively with an adder to perform a...
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6877022 |
Booth encoding circuit for a multiplier of a multiply-accumulate module
A Booth encoding circuit includes a plurality of cells ( 202 a- 202 d ), in which at least one of the cells ( 202 c ) includes a plurality of inputs. The cell also includes a first plurality of...
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6813627 |
Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operands
Integer multiply operations using data stored in an integer register file are performed using multi-media primitive instructions that operate on smaller operands. The present invention performs a...
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6763367 |
Pre-reduction technique within a multiplier/accumulator architecture
An apparatus and method for compressing a reduction array into an accumulated carry-save sum. The reduction array includes a partial product matrix, a carry-save sum, and a constant value row. A...
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6742011 |
Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry
The present invention generally relates to an apparatus and method for efficiently summing the partial product bits produced by a multiplier. Briefly described, in architecture, the apparatus...
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6708193 |
Linear summation multiplier array implementation for both signed and unsigned multiplication
A system and method are disclosed which provide a multiplier comprising a linear summation array that is implemented in a manner that enables both signed and unsigned multiplication to be...
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6684236 |
System of and method for efficiently performing computations through extended booth encoding of the operands thereto
A system of and method for extended Booth encoding of two binary numbers, K and L. A stage of the encoder receives K[2n+1], K[2n], L[2n+1], and C[n−1], N−1≧n≧0, with N being the length of...
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6675186 |
Decibel adjustment device with shift amount control circuit
A decibel level adjustment device that calculates an output signal that is a d decibel multiple of an input signal comprises a plurality of shift circuits, a shift amount control circuit, and...
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6633896 |
Method and system for multiplying large numbers
The present invention provides a computer-implemented method for multiplying two large multiplicands. The method includes generating a plurality of partial products by multiplying each digit of the...
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6629119 |
Arithmetic device and method with low power consumption
An arithmetic device with low power consumption includes master latches, a dynamic range detection unit, slave latches, an operation unit, and a word-length restoration unit. In the arithmetic...
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6622154 |
Alternate booth partial product generation for a hardware multiplier
In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware...
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6523055 |
Circuit and method for multiplying and accumulating the sum of two products in a single cycle
A multiplication accumulation circuit (abbreviated as “MAC”) has five input buses that carry signals for operands A, B, C, D and E, a control bus that carries signals for controlling the...
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6490607 |
Shared FP and SIMD 3D multiplier
A multiplier configured to perform multiplication of both scalar floating point values (X×Y) and packed floating point values (i.e., X 1 ×Y 1 and X 2 ×Y 2 ). In addition, the multiplier may be...
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6484194 |
Low cost multiplier block with chain capability
This application describes a method of multiplying numbers represented in multiple-word chains. The multiplication scheme allows for the multiplication of both signed and unsigned numbers of...
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