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8126954 |
Method and system for avoiding underflow in a floating-point operation
Methods and systems for detecting underflow in a floating-point operation are disclosed. In accordance with an example disclosed method a plurality of comparator circuits and a plurality of logic...
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7593977 |
Method and system for avoiding underflow in a floating-point operation
A method and system for determining whether a result d of a floating-point operation on operands a, b, c is tiny (may underflow) is disclosed. In one embodiment, a prediction whether d is tiny is...
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7454455 |
Apparatus, and system, for efficient and reliable computation of results for mathematical functions
An apparatus and system are provided for efficient computation of reliable results for mathematical functions. The apparatus may include an interface, a control module, and an error module. The...
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7206800 |
Overflow detection and clamping with parallel operand processing for fixed-point multipliers
A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of...
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7197525 |
Method and system for fixed point fast fourier transform with improved SNR
A system and method of improving signal to noise ration (SNR) in a fixed point fast Fourier transform (FFT/IFFT) generates from sample inputs and a twiddle factor butterfly outputs for each stage;...
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7120661 |
Bit exactness support in dual-MAC architecture
An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in...
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6983300 |
Arithmetic unit
An arithmetic unit for adding a plurality of values to define a result, the arithmetic unit including circuitry for receiving the plurality of values; circuitry for adding the plurality of values...
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6457036 |
System for accurately performing an integer multiply-divide operation
A system for accurately and efficiently determining the result of an integer multiple-divide operation having the form of (A*B)/C is disclosed. If the values of A, B, and C provide for an easy...
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6161164 |
Content addressable memory accessed by the sum of two operands
Within a content addressable memory, the latency in a memory access is reduced by combining the steps of effective address generation addition and searching within the content-addressable memory....
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5974432 |
On-the-fly one-hot encoding of leading zero count
A superscalar microprocessor including a floating point unit implements a floating point adder with a leading zero anticipator that predicts the number of leading zeros in the significand sum of...
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5940312 |
Signed binary logarithm system
A method and apparatus for implementing a binary logarithm of most significant bit instruction that operates on an input signed binary number. The input signed binary number includes a fixed number...
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5907498 |
Circuit and method for overflow detection in a digital signal processor having a barrel shifter and arithmetic logic unit connected in series
A digital signal processor (DSP) having a serially connected barrel shifter and arithmetic logic unit and overflow detecting method thereof is disclosed. The barrel shifter of the digital signal...
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5905663 |
Minimal circuit for detecting loss of precision in floating point numbers
A circuit and method for detecting when converting a number from a floating point format to a fixed point format will result in a loss of precision. All bits but the most significant bit of the...
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5801978 |
Overflow detection for integer-multiply instruction
An arithmetic logic unit includes overflow trap logic for an integer-multiply instruction. A multiply unit multiplies a pair of n-bit operands together and produces a n+1 bit result. The low order...
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5745397 |
Addition overflow detection circuit
The invention provides an addition overflow detection circuit which can detect an addition overflow at a high rate even where the output bit number is remarkably smaller than the input bit number...
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5260890 |
Overflow detection system and its circuit for use in addition and subtraction
In an overflow detection circuit for A+B operation, an inverter outputs a value VB ' comprising inverted bits of a numeric part of an addend B. A comparator receives as an input a numeric part VA...
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5231600 |
Overflow detector for anticipating producing invalid operands resulting from performing shift operations on such operands
Overflow detector connects in parallel with a shifter to receive the bits of an operand to be shifted for detecting an overflow condition by defining the location of the operand sign bit and...
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5031135 |
Device for multi-precision and block arithmetic support in digital processors
A device for multi-precision and block arithmetic support in a digital processor including a multiplier for multiplying two signed, unsigned or signed and unsigned binary numbers and having a...
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4941119 |
Method and apparatus for predicting an overflow in an integer multiply
An overflow prediction scheme is provided to operate in parallel with an integer multiply within a computer to predict overflow conditions of the resultant register. The operands to be multiplied...
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