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7574335 Modelling piece-wise continuous transfer functions for digital image processing  
Methods and apparatus, including computer program products, for modelling a non-linear transfer function with a power law function. A transfer function is received. Iteratively, until a termination...
7574561 Method and apparatus for storing a data to memory devices  
A method and apparatus for enhancing performance of parity check in computer readable media is provided. For example, in a RAID (N+1) configuration, a virtual data strip is added for a calculation...
7555691 Apparatus and method for providing near-optimal representations over redundant dictionaries  
Certain exemplary embodiments provide a method comprising a plurality of activities, comprising: automatically: receiving a signal; and via a plurality of iterations, determining, for the received...
7461118 Arithmetic logic unit with merged circuitry for comparison, minimum/maximum selection and saturation for signed and unsigned numbers  
A saturation-capable arithmetic logic unit (ALU) includes a general-purpose comparator coupled to receive a data value and a saturation threshold value during a saturation operation. Using the...
7453960 LDPC encoder and encoder and method thereof  
A decoder for decoding low-density parity-check codes comprises a first calculator to calculate LLrR ml , for each parity check equation, at iteration i−1. A detector detects LLrR ml , at...
7412475 Error detecting arithmetic circuits using hexadecimal digital roots  
Embodiments of the invention are directed to circuits and techniques for computer processor register integrity checking employing digital roots, and hexadecimal digital roots (HDRs) in particular,...
7340003 Multi-mode iterative detector  
A storage system for storing data on a storage medium includes an encoder, a linear block encoder, a write circuit, a read circuit, a channel decoder, and a soft linear block code decoder. In a...
7035891 Reduced-hardware soft error detection  
A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction,...
7028067 Generation of mask-constrained floating-point addition and subtraction test cases, and method and system therefor  
A method and system for generating numerical test cases for testing binary floating-point arithmetic units for addition and subtraction operations, in order to verify the proper operation of the...
7020550 Vehicle electronic controller  
A vehicle electronic controller for checking a control microcomputer with a common monitoring IC, which is used in different vehicles. The vehicle electronic controller includes a control...
6914983 Method for checking modular multiplication  
The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in...
6829308 Satellite communication system utilizing low density parity check codes  
An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message...
6779014 Cyclic step by step decoding method used in discrete fourier transform cyclic code of a communication system  
Discrete Fourier transformation is applied to an analog system so that a signal be transfering, the analog data can be corrected before being quantized and after being transferred and received. In...
6772185 Time-series predicting method using wavelet number series and device thereof  
An object is to provide a time-series prediction method and apparatus utilizing wavelet coefficient series which can accurately predict a prediction value of an original time series. When a...
6754542 Control arithmetic apparatus and method  
A control arithmetic device includes a subtracting section, disturbance application detecting section, error correction amount calculating section, error correction amount convergence calculating...
6718276 Method and apparatus for characterizing frequency response on an error performance analyzer  
A method and apparatus for characterizing frequency response of a device under test (DUT) is disclosed. A repeated base bit pattern is received, the base bit pattern including a first transition...
6643678 Correction of code drift in a non-coherent memory  
An apparatus and method allow receivers to quickly acquire a pseudorandom noise signal. A receiver can include a Doppler correction circuit, which permits correlation data with frequency shift in...
6519620 Saturation select apparatus and method therefor  
A saturation select apparatus and method are implemented. Late stage logic blocks in an adder are provided which combine saturation select control signals with sum generating signals. A first...
6499046 Saturation detection apparatus and method therefor  
An apparatus for saturation detection and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an output from an adder receiving a pair of input...
6427160 Method and system for testing floating point logic  
In a computer system, a method and system for verifying whether a floating-point logic unit correctly directly rounds floating-point numbers when conducting multiplication, square root, and...
6370672 Determining the received data rate in a variable rate communications system  
The present invention comprises methods and apparatus for determining the rate at which data was encoded when such data is received at a receiver. According to the present invention, the rate is...
6330660 Method and apparatus for saturated multiplication and accumulation in an application specific signal processor  
An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation...
6243726 Electronic calculating apparatus utilizing input and display of expressions in textbook and single line formats  
Objects of the present invention are to realize that a plurality of mathematical expressions are inputted and displayed within the same screen in textbook book format, and that a plurality of...
6108678 Method and apparatus to detect a floating point mantissa of all zeros or all ones  
A method to detect a normalized data field of all zeros or all ones includes receiving a control field and a data field, dividing the data field into segments, and performing detections on each...
6101523 Method and apparatus for controlling calculation error  
A method and an apparatus for controlling calculation error produced by the accumulation error due to digit truncation in a non-integer computation. The error is eliminated by controlling the...
6047304 Method and apparatus for performing lane arithmetic to perform network processing  
A method and apparatus for processing network packets is disclosed. A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions...
5953240 SIMD TCP/UDP checksumming in a CPU  
A CPU adapted to calculate a checksum simultaneously on multiple values packed into a single register. An adder is provided which adds a number of values packed into a first register to a number of...
5949677 Control system utilizing fault detection  
A control architecture having improved fault detection and correction capabilities is disclosed. The system comprises primary and monitor control systems, each having an associated control signal....
5889689 Hierarchical carry-select, three-input saturation  
There is disclosed a first adder subtractor combines the largest positive number or largest negative number capable of being represented by the number of bits in the datapath, as determined by the...
5880982 Error detecting digital arithmetic circuit  
A digital arithmetic circuit includes an inverting circuit connected to a digital circuit in which errors are to be detected. An operand input to the circuit produces an output result in a first...
5872730 Computerized correction of numeric data  
Apparatus and a method is described for correcting a set of stored digital representations of numbers having an estimable error probability distribution where there is at least one known arithmetic...
5822786 Apparatus and method for determining if an operand lies within an expand up or expand down segment  
Dedicated parallel comparators perform expand up or expand down segment limit checks for memory accesses. A first three-input comparator has as inputs the complement of the segment limit, the...
5808889 System and method for identifying and correcting computer operations involving two digit year dates  
A system and method for identifying and correcting computer operations involving two digit year dates. The system includes: a computer and a routine for searching for a subtraction, comparison and...
5742533 Method and apparatus for modulus error checking  
Apparatus and method for checking the final result of a computer implemented floating point arithmetic unit employs an effective subtract signal, which is already in use and logically required to...
5689727 Disk drive with pipelined embedded ECC/EDC controller which provides parallel operand fetching and instruction execution  
An intelligent disk drive having error detection and correction capability employs an embedded error correction controller with a pipelined architecture for performing error correction under...
5689721 Detecting overflow conditions for negative quotients in nonrestoring two's complement division  
A method of detecting anomalous overflow conditions is used, in an exemplary embodiment, in implementing in a 486-type microprocessor, nonrestoring two's complement division for negative quotients...
5677860 Overflow and underflow processing circuit of a binary adder  
Two input data X (7), Y (7), . . . , X (0), Y (0) are input to a plurality of full adders, and an overflow/underflow signal of each full adder is input to a full adder of a higher level. An...
5673210 Signal restoration using left-sided and right-sided autoregressive parameters  
Signal reconstruction methods reconstruct a missing portion of a signal from a first known portion of the signal preceding the missing portion, and a second known portion of the signal succeeding...
5657253 Apparatus for monitoring the performance of a microprocessor  
An apparatus for measuring and monitoring various parameters that contribute to the performance of a processor includes a pair of programmable event counters for counting any two independent events...
5600658 Built-in self tests for large multiplier, adder, or subtractor  
A method of testing a two-input multiplier, adder, or subtractor implementation for stuck-at faults includes a multi-step procedure for iteratively exercising all input and output permutations, and...
5566193 Method and apparatus for detecting and preventing the communication of bit errors on a high performance serial data link  
A method and apparatus for communicating serial data at very high actual and effective data rates with a high probability of detecting single and multiple bits errors, even burst errors. The method...
5504697 Limiter circuit producing data by use of comparison in effective digit number of data  
Disclosed herein is a limiter circuit for limiting an output data to a limit value when an input data exceeds in value the limit value. The limiter circuit includes an encoder responding to the...
5467296 High-speed small digital multiplier  
A digital multiplier absolutizes a multiplicand and a multiplier for decreasing component bits thereof, and multiplies the absolutized multiplicand by the absolutized multiplier for producing a...
5448509 Efficient hardware handling of positive and negative overflow resulting from arithmetic operations  
A computer system provides handling of positive and negative overflow. A first arithmetic operation is performed on a first n-bit unsigned binary operand and a second n-bit signed binary operand to...
5444638 Ambulatory monitor ECG pulse calibration method  
An ECG waveform calibration method combines ECG channel calibration pulses to form combined calibration pulses. The combined channel pulses are filtered to select valid combined pulses. The...
5432795 System for reporting errors of a translated program and using a boundry instruction bitmap to determine the corresponding instruction address in a source program  
In a situation where a first computer program has been translated to obtain a second computer program, an error occurring during execution of the second computer program is reported in the context...
5430852 Control transfer method in system with multiple arithmetic units each with independent microprogram control by transferring start address and branch condition codes  
A microprogram control system has first and second microprogram control units and first and second arithmetic circuits corresponding to the first and second microprogram control units,...
5422805 Method and apparatus for multiplying two numbers using signed arithmetic  
A signed arithmetic data processing system (20) detects a multiply (MUL) or a multiply-and-accumulate (MAC) instruction in which a multiplier and a multiplicand each assume their respective maximum...
5369438 Apparatus for processing image motion compensation information for an image processing system  
An apparatus for processing image motion compensation information for an image processing system, which can add image motion compensation information and assign the bit number suitable for a...
5321844 Method for error correction of software errors in a communication system  
In a communication system having connector modules, a switching network serving for the through-connection of calls, a central signal channel, as well as a multiprocessor system for central...
Matches 1 - 50 out of 103 1 2 3 >